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Published 20 hours ago • verified publisher icon CoenraadS

Verilog case statements mismatch

Open BEN425 opened this issue 3 years ago • 1 comments

It can't match endcase with case and casex in verilog, but works fine with casez

螢幕擷取畫面 2021-12-24 230903

BEN425 avatar Dec 24 '21 15:12 BEN425