added verilog module for LSB

[092vk]

Fixes #560

Describe the changes you have made in this PR -

1. Added the verilog moduel for LSB
2. Replaced the generateVerilog() with moduleVerilog()

Note: Please check Allow edits from maintainers. if you would like us to assist in the PR.

Summary by CodeRabbit

• Bug Fixes

  • Corrected a typo in the input size property for improved accuracy.

• New Features

  • Enhanced Verilog module generation for LSB functionality, providing a more comprehensive and parameterized output.

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Walkthrough

The changes correct a property typo in the LSB module, remove the existing generateVerilog method, and introduce a new static moduleVerilog method. This method returns a complete Verilog module definition for the LSB circuit element, implementing explicit parameters, ports, and logic for determining the least significant set bit.

Changes

Files	Change Summary
src/simulator/src/modules/LSB.js	Fixed typo (intputSize to inputSize), removed generateVerilog, added moduleVerilog with full Verilog module definition for LSB.

Assessment against linked issues

Objective (Issue #)	Addressed	Explanation
Implement Verilog module for LSB circuit element (#560)	✅
Implement Verilog modules for SR Flip Flop, JK Flip Flop, ALU, D-Latch, ForceGate (#560)	❌	Only the LSB module is implemented; other modules are not addressed in this change.

Assessment against linked issues: Out-of-scope changes

Code Change	Explanation
Correction of property name typo from intputSize to inputSize (src/simulator/src/modules/LSB.js)	This typo fix is adjacent to the main objective but not explicitly mentioned in the linked issue.

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