Added pre condition in the verilog module

[092vk]

Fixes #561

Describe the changes you have made in this PR -

1. Added the pre condiiton logic in the verilog module
2. Made the verilog module consistent to the circuit simulation logic

Note: Please check Allow edits from maintainers. if you would like us to assist in the PR.

Summary by CodeRabbit

• Bug Fixes
  • Improved the T flip-flop’s asynchronous reset so preset/unknown cases are handled more accurately, reducing simulation inaccuracies.
  • Refined enable and toggle semantics so the flip-flop now reliably holds or toggles only when enabled and t is high, while maintaining complementary q/q_inv outputs after reset.

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[coderabbitai[bot]]

Walkthrough

The Verilog string in TflipFlop.js was updated to change reset and toggle semantics: asynchronous reset now assigns outputs based on pre, enable gating replaces previous en==0 path, and the always block and port declarations were restructured to match simulator logic.

Changes

Cohort / File(s)	Change Summary
T flip-flop Verilog update src/simulator/src/sequential/TflipFlop.js	Rewrote the generated Verilog module string in moduleVerilog(): updated port declarations (input clk, a_rst, en; input [WIDTH-1:0] t, pre;), changed async reset to assign q = pre and q_inv = ~pre, replaced previous enable/toggle paths with explicit en-gated toggle and hold branches, wrapped always block with begin...end, and added inline comments.

Estimated code review effort

🎯 2 (Simple) | ⏱️ ~10 minutes

Assessment against linked issues

Objective	Addressed	Explanation
Fix errors in Verilog modules and ensure consistency with simulator logic (#561)	✅
Implement preset (pre) handling in flip-flop Verilog modules (#561)	✅
Ensure flip-flop enable and toggle semantics match simulator behavior (#561)	✅

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