Added Verilog Module to ALU

[092vk]

Fixes #560

Describe the changes you have made in this PR -

1. Added the verilog module for ALU
2. All the cases were handled according to the circuit simulation design
3. An inconsistency was done in case of ctr = 3, which is a buffer or not-used ctr statement, for this case in simulation model the results are preserved and not changed but in verilog module the results are made 0. This is done to keep ALU combinational in nature and not sequential.

Note: Please check Allow edits from maintainers. if you would like us to assist in the PR.

Summary by CodeRabbit

• New Features
  • Added Verilog export for the ALU, generating a parameterized module (configurable width) with inputs a, b, ctr and outputs out, cout. Supports common ops (bitwise, add/sub, compare) via control codes, with defaults for unspecified cases. Existing simulation behavior remains unchanged.

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[coderabbitai[bot]]

Walkthrough

Adds a static ALU.moduleVerilog() method that returns a Verilog module string describing an ALU with WIDTH parameter, inputs a, b, ctr; outputs out, cout; and a case over ctr implementing ops (AND, OR, ADD, reserved, A&~B, A|~B, SUB, A<B). No runtime logic changes.

Changes

Cohort / File(s)	Summary
ALU Verilog export src/simulator/src/modules/ALU.js	Added static moduleVerilog() returning a WIDTH-parameterized Verilog ALU module implementing 8 ctrl operations; default zeros; does not alter resolve() or other runtime behavior.

Estimated code review effort

🎯 2 (Simple) | ⏱️ ~10 minutes

Assessment against linked issues

Objective	Addressed	Explanation
ALU: Provide Verilog module (#560)	✅
SR Flip Flops: Provide Verilog module (#560)	❌	No related changes present in this diff.
JK Flip Flops: Provide Verilog module (#560)	❌	No related changes present in this diff.
D-Latch: Provide Verilog module (#560)	❌	No related changes present in this diff.
ForceGate, LSB/MSB: Provide Verilog modules (#560)	❌	No related changes present in this diff.

Suggested reviewers

• JoshVarga
• niladrix719

✨ Finishing Touches

• [ ] 📝 Generate Docstrings

🧪 Generate unit tests

• [ ] Create PR with unit tests
• [ ] Post copyable unit tests in a comment

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