Better handling of non-flat register spaces

[sorear]

x64, riscv, and arm7 have a set of 8 registers which can be used by shorter forms of instructions, and should be preferred for variables that are frequently accessed. To some extent the existing register renaming support can handle this, but it has undesirable assumptions (the link register is always used first, but the ISA link register is not a preferred GPR on either riscv or arm7) and the static partitioning of temporaries between phases that need them also makes this difficult. I don't have a good idea what would be changed to make this happen.