learn-fpga
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BrunoLevy
Debug support re-using existing blocks
It would be very nice to have GDB debug support over JTAG using the existing work in DM/DMI/OpenOCD. A good example where the RISC-V debug module was added to the Ibex RV32IMC can be found in these last three commits:
https://github.com/majbthrd/ibex/commits/add_debug
Specifically:
https://github.com/majbthrd/ibex/commit/371c4bcbe5763261cd08dd1500a0fde320a93cfa
It is very nice to build/upload and visually start debugging (for example VSCode) within 1 second.
Yes it is a nice option to add. It will probably require to add some logic in the processor, I am not familiar with how debugging works with RISC-V, but it is something I may add in the future (once I understand how it works !). Is there a tutorial / explanation somewhere I could start from ?
