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Title: ESP32-S3 (N8R8 OPI PSRAM) + ILI9341: TFT_eSPI crashes with StoreProhibited (EXCVADDR: 0x00000010) in tft.begin()

Open Stenliczz opened this issue 7 months ago • 11 comments

Hello Bodmer,

I'm encountering a persistent crash when trying to use TFT_eSPI with an ESP32-S3 on a Freenove ESP32-S3 WROOM N8R8 board. The crash is a Guru Meditation Error: Core 1 panic'ed (StoreProhibited). Exception was unhandled. EXCVADDR: 0x00000010 occurring during the tft.begin() call.

I've confirmed that PSRAM (8MB OPI) is active in the firmware when using the freenove_esp32_s3_wroom board definition with the latest PlatformIO espressif32 platform.

Crucially, the Adafruit_ILI9341 library works perfectly on the exact same hardware, pins, and board configuration (Freenove ESP32-S3 WROOM with PSRAM active). This strongly suggests the issue is specific to TFT_eSPI's interaction with the ESP32-S3 SPI/FSPI.

Additionally, TFT_eSPI (v2.5.30) does work without crashing if I use an older ESP32 Arduino Core (2.0.11 via PlatformIO espressif32 @ 6.4.0) with a generic esp32-s3-devkitc-1 board definition. However, with this older setup, PSRAM is reported as "No PSRAM" in the build and fails to initialize at runtime, making it unsuitable for my project.

This leads me to believe the crash might be related to TFT_eSPI's handling of ESP32-S3 with newer Arduino Core versions (>2.0.14, as some online discussions suggest).

Hardware Details:

Microcontroller: ESP32-S3 (on Freenove ESP32-S3 WROOM N8R8 board - 8MB Flash, 8MB OPI PSRAM) Display: ILI9341 Pins Used: MOSI: GPIO 11

platformio.ini.txt

main.cpp.txt

crash log.txt

SCLK: GPIO 12 CS: GPIO 10 DC: GPIO 9 RST: -1 (Not connected, display has pull-up) Software Environment (PlatformIO) for Crashing TFT_eSPI setup:

platform = espressif32 (resolves to 6.10.0, using framework-arduinoespressif32 @ 3.20017.241212+sha.dcc1105b which is based on Arduino Core ~2.0.17) board = freenove_esp32_s3_wroom (Build log confirms "8MB Flash / 8MB PSRAM") TFT_eSPI versions tested that crash: 2.5.43, 2.5.30

Working Adafruit_ILI9341 Configuration (for comparison):

PlatformIO platform = espressif32 (latest, 6.10.0) PlatformIO board = freenove_esp32_s3_wroom (Build log confirms "8MB Flash / 8MB PSRAM") Pins: MOSI=11, SCLK=12, CS=10, DC=9, RST=-1 This setup works perfectly.

[env:adafruit_freenove_s3_test_working] platform = espressif32 board = freenove_esp32_s3_wroom framework = arduino monitor_speed = 115200 lib_deps = adafruit/Adafruit ILI9341 adafruit/Adafruit GFX Library

main.cpp #include <Arduino.h> #include <Adafruit_GFX.h> #include <Adafruit_ILI9341.h> #include <SPI.h>

#define TFT_CS 10 #define TFT_DC 9 #define TFT_RST -1

Adafruit_ILI9341 tft = Adafruit_ILI9341(TFT_CS, TFT_DC, TFT_RST); // Uses default SPI pins (MOSI=11, SCLK=12 for S3 devkit variant)

void setup() { Serial.begin(115200); for (int i = 0; i < 10 && !Serial; ++i) { delay(100); } Serial.println("\n>>> Adafruit ILI9341 Test on Freenove ESP32-S3 WROOM <<<"); if(psramFound()){ Serial.printf("PSRAM Total: %u, Free: %u\n", ESP.getPsramSize(), ESP.getFreePsram()); } else { Serial.println("PSRAM NOT FOUND!"); } tft.begin(); tft.setRotation(1); tft.fillScreen(ILI9341_MAGENTA); tft.setCursor(10, 50); tft.setTextColor(ILI9341_WHITE); tft.setTextSize(2); tft.println("Adafruit + Freenove S3 WORKS!"); Serial.println("Adafruit display sketch finished setup. Display works."); } void loop() {}

Stenliczz avatar May 24 '25 09:05 Stenliczz

i believe the bug here is that the macro to compute the spi register base address is just broken.

see REG_SPI_BASE at https://github.com/Bodmer/TFT_eSPI/blob/5793878d24161c1ed23ccb136f8564f332506d53/Processors/TFT_eSPI_ESP32_S3.h#L31, and later where offsets are computed and stores are executed (e.g. into _spi_user): https://github.com/Bodmer/TFT_eSPI/blob/5793878d24161c1ed23ccb136f8564f332506d53/Processors/TFT_eSPI_ESP32_S3.h#L116

someone complained a while back about this for the esp32c3 in the arduino core with no resolution at https://github.com/espressif/arduino-esp32/issues/10908.

@Bodmer also complained about a related issue at https://github.com/espressif/esp-idf/issues/8010.

upstream esp-idf is defining REG_SPI_BASE in such a way that for TFT_eSPI + esp32s3, the register will evaluate to 0 + some offset, e.g. EXCVADDR here is probably offset 0x10, which is supposed to be SPI_USER_REG: https://github.com/espressif/esp-idf/blob/release/v5.5/components/soc/esp32s3/include/soc/soc.h#L36

my local workaround is simply to add #undef REG_SPI_BASE in https://github.com/Bodmer/TFT_eSPI/blob/5793878d24161c1ed23ccb136f8564f332506d53/Processors/TFT_eSPI_ESP32_S3.h#L31.

@Bodmer any thoughts on a real fix for this?

mischief avatar Jun 02 '25 03:06 mischief

same problem here :(

//edit: @Stenliczz @mischief

libdeps\esp32-s3-devkitc-1\TFT_eSPI\Processors\TFT_eSPI_ESP32_S3.h

github copilot with claude 4 add line 26 to 40 ..... and for me it"s working!

// Fix IDF problems with ESP32S3
// Note illogical enumerations: FSPI_HOST=SPI2_HOST=1   HSPI_HOST=SPI3_HOST=2
#if CONFIG_IDF_TARGET_ESP32S3
  // Fix ESP32C3 IDF bug for missing definition (FSPI only tested at the moment)
  #undef REG_SPI_BASE  // Fix ESP32-S3 crash: REG_SPI_BASE evaluates to 0x00000000
  #ifndef REG_SPI_BASE //                      HSPI                 FSPI/VSPI
    #define REG_SPI_BASE(i) (((i)>1) ? (DR_REG_SPI3_BASE) : (DR_REG_SPI2_BASE))
  #endif

  // Fix ESP32S3 IDF bug for name change
  #ifndef SPI_MOSI_DLEN_REG
    #define SPI_MOSI_DLEN_REG(x) SPI_MS_DLEN_REG(x)
  #endif

#endif

fabse-hack avatar Jun 08 '25 09:06 fabse-hack

i don't think we need "insight" from "claude 4" here, but rather some human understanding of the intent of upstream espressif's change of this API. a workaround in this repo for the broken upstream interface is ok, but what you have shared here is totally out of touch.

mischief avatar Jun 08 '25 16:06 mischief

@mischief hmmmm okay, sorry..... i just beginn today with arduino ... esp32 s3, ili9341, lvgl and much problems.....

fabse-hack avatar Jun 08 '25 22:06 fabse-hack

my local workaround is simply to add #undef REG_SPI_BASE in

TFT_eSPI/Processors/TFT_eSPI_ESP32_S3.h

Line 31 in 5793878 #define REG_SPI_BASE(i) (((i)>1) ? (DR_REG_SPI3_BASE) : (DR_REG_SPI2_BASE))

@mischief THANK YOU!!!

This workaround got my project running again! I've been banging my head against the wall for an embarrassingly long time and your workaround saved me.

wolffinator avatar Jun 13 '25 02:06 wolffinator

This stopped the crash for me, but the display is no longer working now.

NeariX67 avatar Jul 03 '25 15:07 NeariX67

Same for me. The program no longer crashes after unregistering REG_SPI_BASE but I get a blank display no matter what I do. Does anyone have this library working with ESP32S3 right now?

mike-lloyd03 avatar Jul 08 '25 23:07 mike-lloyd03

Someone solved this issue. Have a look: https://www.youtube.com/watch?v=7FeBbqSW834&t=676s

sovran82 avatar Jul 28 '25 10:07 sovran82

Hi there. I watched the video and it didn't really explain how to fix the crash, nor the display staying white. On some other issue in this repo, someone mentioned you should change https://github.com/Bodmer/TFT_eSPI/blob/master/Processors/TFT_eSPI_ESP32_S3.h#L83 to #define SPI_PORT 3 for the ESP32-S3 to get rid of the panic. It fixed the panic, but also made the screen show nothing anymore in my case, I fixed it by changing it to #define SPI_PORT 2

tommywienert avatar Jul 30 '25 20:07 tommywienert

I found a possible bug in v3.X.X, you must set pin TFT_MISO to a nonzero pin. If not, in v3.X.X esp32 core, this will cause the spi register (*_spi_cmd) never to refresh, spi port is blocked (2.0.14 not). https://github.com/Bodmer/TFT_eSPI/blob/5793878d24161c1ed23ccb136f8564f332506d53/Processors/TFT_eSPI_ESP32_C3.h#L541-L546 And if you don't define TFT_MISO or TFT_MISO == -1, this code will set it to TFT_MOSI, then port will be blocked. https://github.com/Bodmer/TFT_eSPI/blob/5793878d24161c1ed23ccb136f8564f332506d53/Processors/TFT_eSPI_ESP32_C3.h#L316-L321

The attched tarball is my minimum modified code and an example. TFT_eSPI_c3.zip

niu541412 avatar Aug 01 '25 20:08 niu541412

@niu541412 do you think you could open a PR so this can get fixed upstream?

Edit: Actually, I think this repo may have been abandoned. There hasn't been a commit for over a year.

mike-lloyd03 avatar Aug 06 '25 22:08 mike-lloyd03