GPU component manufacture impacts

[da-ekchajzer]

Problem

No GPU components are implemented. It makes it to impossible to evaluate high performance compute server. Some services cannot be assessed :

• IA
• Cryptomining
• High performance computing.

Solution

We need resources on scope 3 impacts of GPUs. Are GPUs manufacture impacts depend on their die size ?

Additional context or elements

Linked with this issue : https://github.com/Boavizta/environmental-footprint-data/issues/50

[da-ekchajzer]

ECODIAG APPROACH

Link : https://ecoinfo.cnrs.fr/ecodiag-calcul/

gpu: {
    label_fr:           'GPU puissant',
    label_en:           'Powefull GPU',
    regex:              /(carte graphique|gpu)/i,
    grey_CO2:           {mean:60,std:hypot([0.6,0.6])},
                            // It highly depends on the GPU, but assuming only powerful GPU's are counted,
                            // and provided that on average the footprint of a motherboard is about 113 kgCO2e
                            // this choice seems reasonable.
                            // Moreover, in NumEU study, a desktop game console is estimated at 170 kgCO2e,
                            // so assigning 35% for the GPU seems to be reasonable too.
                            // Uncertainties:
                            //  - 60% for the LCA
                            //  - 60% for the variation across GPUs
    duration:            4,
    yearly_consumption:  0,
    models: {
      default: {
        label_fr: 'Défaut',
        regex: /(carte graphique|graphic.*card|\Wgtx\W|\Wrtx\W|\Wquadro\W|\Wtitan\W|\Wgeforce\W|\Wgpu\W)/i
      }
    }
  },

};

[samuelrince]

First approximation would be to consider a GPU as "a compute chip" + "a memory bank" + "a board" and apply adapted formulas from CPU, RAM and a fix value for the board.

Compute chip part

The original CPU formula to compute manufacturing impact is:

$$ \text{CPU}_\text{manufacture}^\text{criteria} = (\text{CPU}_{\text{core units}} * \text{CPU}_{\text{die size per core}} + 0.491 ) * \text{CPU}_\text{manufacture die}^\text{criteria} + \text{CPU}_\text{manufacture base}^\text{criteria} $$

We can rewrite it for GPU components:

$$ \text{GPU}_\text{manufacture chip}^\text{criteria} = (\text{GPU}_{\text{die size}} + 0.491 ) * \text{CPU}_\text{manufacture die}^\text{criteria} + \text{CPU}_\text{manufacture base}^\text{criteria} $$

⚠️ we keep the CPU manufacturing impact factors for now.

Memory part

We can keep the same formula (using highest density value if unknown):

$$ \text{GPU}_\text{manufacture memory}^\text{criteria} = (\text{GPU}_{\text{memory capacity}} / \text{RAM}_{\text{density}}) * \text{RAM}_\text{manufacture die}^\text{criteria} + \text{RAM}_\text{manufacture base}^\text{criteria} $$

⚠️ we keep the RAM manufacturing impact factors for now.

Board part

For the board part I guess we can take constants from the motherboard and maybe divide them by 2 (or 3)?. I guess that given the precision of the above formulas it would be fair to say that a GPU board is around half (or one-third) the size of a motherboard and contains half (or one-third) the number of electronic components.

$$ \text{GPU}_{\text{manufacture board}}^{\text{criteria}} = \frac{1}{2} * \text{motherboard}_{\text{manufacture}}^{\text{criteria}} $$

Total manufacturing impact

$$ \text{GPU}_{\text{manufacture}}^{\text{criteria}} = \text{GPU}_{\text{manufacture chip}}^{\text{criteria}} + \text{GPU}_{\text{manufacture memory}}^{\text{criteria}} + \text{GPU}_{\text{manufacture board}}^{\text{criteria}} $$

Let me know what you think on this approach. 🤗

Edit: Change latex formula because GitHub can't render them properly...

[samuelrince]

After a great discussion with @ThibaultPirson we will make some updates to the proposed formulas above and we will start with the "board part".

The objective here is to quantify the contribution of the PCB manufacturing for the GPU.

Board manufacturing formula

Hypothesis:

• The PCB impact scales with the size (area), number of layers and technology used.
• The number of layers will be constant equals to 4.
• We will consider that the PCB is made of epoxy based substrate (FR-4).

So the final GPU board manufacturing formula will only depend on the $area$ as a first approximation.

$$ \text{GPU}_{\text{manufacture board}}^{\text{criteria}}(area) = area * \text{PCB}_{\text{manufacture}}^{\text{criteria}} $$

With the followings:

• $area$ in $m^2$
• $\text{PCB}_{\text{manufacture}}^{\text{GWP}}$ in $kgCO2eq.m^{-2}$
• $\text{PCB}_{\text{manufacture}}^{\text{ADP}}$ in $kgSBeq.m^{-2}$
• $\text{PCB}_{\text{manufacture}}^{\text{PE}}$ in $MJ.m^{-2}$

Estimate impacts factors

Liu et al., 2014

For a 4-layered PCB epoxy based substrate (FR-4) we can retain the GWP impact factor per square meter:

$$ (\text{PCB}_{\text{manufacture}}^{\text{GWP}})_\text{Liu et al., 2014} = 39.2\ kgCO2eq.m^{-2} $$

Ozkan et al., 2018

The study compares there results with Liu et al., 2014. Still with a 4-layered FR-4 PCB.

$$ (\text{PCB}_{\text{manufacture}}^{\text{GWP}})_\text{Ozkan et al., 2018} = 18.6\ kgCO2eq.m^{-2} $$

$$ (\text{PCB}_{\text{manufacture}}^{\text{ADP}})_\text{Ozkan et al., 2018} = 1.71.10^{-3}\ kgSBeq.m^{-2} $$

Nassajfar et al., 2021

Still with a 4-layered FR-4 PCB.

$$ (\text{PCB}_{\text{manufacture}}^{\text{GWP}})_\text{Nassajfar et al., 2021} = 34.8\ kgCO2eq.m^{-2} $$

Conclusion and critics

We can take the following impact factors for now:

• GWP of 39.2 kgCO2eq./m2 (max value)
• ADP of 1.71e-4 kgSBeq./m2 (only one value)
• PE ???? none of the above study mention this impact factor afaik.

We can consider these impact factors as lower bounds because, from what I have seen, GPU boards tend to be from 8 to 14 layers PCB. Here we have impact factors for 4 layered PCB only. Any input on this part to estimate for PCBs with more layers will be a great help.

Let me know if you have any comments, I'll try to do the same work for memory and chip parts soon!

Thanks again @ThibaultPirson for sharing his knowledge on this subject ! 🤗|

Edit: Change latex formula because GitHub can't render them properly...

[da-ekchajzer]

Thank you for this work !

I was wondering if we could open 1 issue per component, since all features of the API will benefit from these improvements ? It would also be easier to list all available impact factors for each component. I think we could also open one for SSD and HDD sine we have new data sources that could be used (even if it is not related to GPU).

For the motherboard, we were wondering how could we use ADPf (given in MJ) to retrieve an impact factor for PE ? I guess that the main difference is that PE will also account for the primary energy produce by renewable sources. I'll try to dig on this subject. Maybe I could ask the LCA experts on Boavizta chat.

We could capitalize on this aggregation of impact factors sources to:

• Add impacts criteria, particularly water. I can't see if any of the impact acronyms correspond to water use for motherboard ?
• Add error margins (related to #147)
• Understand the variability induced by the number of layers on a PCB

I will try to dig down myself and ping some LCA experts to get these data sources.

[samuelrince]

Still in the process of untanggling all impact factors of component formulas. Here is the actual state for CPUs. For Boavizta members only, the original document is here.

CPU Manufacturing Formula

Die

Scope and hypotheses:

• Wafer substrate production
• Front-end process (FEOL)
• Back-end process (BEOL)

$$ \mathbf{impact\_cpu\_die}(die\_size) = die\_size * \mathbf{IMP\_CPU\_DIE} $$

IMP_CPU_DIE:

• gwp = 1.97E+00 kg CO2 eq. / (cm2 of die size)
• adp = 5.87E-07 kg Sb eq. / (cm2 of die size)
• pe = 2.65E+01 MJ / (cm2 of die size)

Socket

Scope and hypotheses:

• The amount of gold used, estimated at 0.36 g

$$ \mathbf{impact\_cpu\_socket} = \mathbf{IMP\_CPU\_SOCKET} $$

IMP_CPU_SOCKET:

• gwp = 5.67E+00 kg CO2 eq.
• adp = 1.99E-02 kg Sb eq.
• pe = 8.78E+01 MJ

Transportation

Scope and hypotheses:

• From wafer substrate production to front-end process
  • Estimated to be 10,000 km by airplane
• From front-end process to back-end process
  • Estimated to be 10,000 km by airplane
• [TO CHECK] From end assembly to end location
  • Estimated to be 10,000 km by airplane

$$ \mathbf{impact\_cpu\_transportation} = \mathbf{IMP\_CPU\_TRANSPORTATION} $$

IMP_CPU_TRANSPORTATION:

• gwp = 3,45E-01 kg CO2 eq.
• adp = 4.33E-08 kg Sb eq.
• pe = 5.33E+00 MJ

Packaging

??? No mention of a packaging impact.

Heat sink

Scope and hypotheses:

• ??? → Database KPI4DCE (Schöd-well et al. 2018)

$$ \mathbf{impact\_cpu\_heat\_sink} = \mathbf{IMP\_CPU\_HEAT\_SINK} $$

IMP_CPU_HEAT_SINK:

• gwp = 3.12E+00 kg CO2 eq.
• adp = 5.19E-04 kg Sb eq.
• pe = 6.33E+01 MJ

Aggregated impacts

$$ \begin{align*}    \mathbf{impact\_cpu}(die\_size) =\ &\mathbf{impact\_cpu\_die}(die\_size) \    &+ \mathbf{impact\_cpu\_socket} \ &+ \mathbf{impact\_cpu\_transportation} \ &+ \mathbf{impact\_cpu\_heat\_sink} \ \end{align*} $$

Source: Green Cloud Computing

I feel like all the sub impacts listed for CPU manufacturing also apply for GPU "compute chip" manufacturing. Does anyone have an opinion on that?

$$ \begin{align*} \mathbf{GPU}_{\text{manufacture compute chip}}(die\_size) =\ &\mathbf{impact\_cpu\_die}(die\_size) \ &+ \mathbf{impact\_cpu\_socket} \ &+ \mathbf{impact\_cpu\_transportation} \ &+ \mathbf{impact\_cpu\_heat\_sink} \ \end{align*} $$

[samuelrince]

Correction from the previous message. When computing the impacts for the compute chip in a GPU, we should not include the "socket" part as it is soldered on the board directly. Thus, the formula is:

$$ \begin{align*} \mathbf{GPU}_{\text{manufacture compute chip}}(die\_size) =\ &\mathbf{impact\_cpu\_die}(die\_size) \ &+ \mathbf{impact\_cpu\_transportation} \ &+ \mathbf{impact\_cpu\_heat\_sink} \ \end{align*} $$

[samuelrince]

RAM Manufacturing Formula

Die

Scope and hypotheses:

• Wafer substrate production
• Front-end process (FEOL)
• Back-end process (BEOL)

$$ \mathbf{impact\_ram\_die}(capacity, density) = \frac{capacity}{density} * \mathbf{IMP\_RAM\_DIE} $$

With the $capacity$ in GB and $density$ in GB/cm2. If the $density$ is unknown we can take the average value suggested in the study for 20nm of 15.01Gbit/cm2.

IMP_RAM_DIE:

• gwp = 2.20E+00 kg CO2 eq. / cm2
• adp = 6,30E-05 kg Sb eq. / cm2
• pe = 2.73E+01 MJ / cm2

Transportation

Scope and hypotheses:

• From wafer substrate production to front-end process
  • Estimated to be 10,000 km by airplane
• From front-end process to back-end process
  • Estimated to be 10,000 km by airplane
• [TO CHECK] From end assembly to end location
  • Estimated to be 10,000 km by airplane

$$ \mathbf{impact\_ram\_transportation} = \mathbf{IMP\_RAM\_TRANSPORTATION} $$

IMP_RAM_TRANSPORTATION:

• gwp = 2.99E+00 kg CO2 eq.
• adp = 3.75E-07 kg Sb eq.
• pe = 4.61E+01 MJ

PCB

Scope and hypotheses:

• For one module, 4192 mm2 of PCB (133.48 [length] x 31.40 [width])

$$ \mathbf{impact\_ram\_pcb} = \mathbf{IMP\_RAM\_PCB} $$

IMP_RAM_PCB:

• gwp = 1,77E+00 kg CO2 eq.
• adp = 6.24E-05 kg Sb eq.
• pe = 2.07E+01 MJ

Gold connectors

Scope and hypotheses:

• For one module, 29.35 mg of gold

$$ \mathbf{impact\_ram\_gold} = \mathbf{IMP\_RAM\_GOLD} $$

IMP_RAM_GOLD:

• gwp = 4,64E-01 kg CO2 eq.
• adp = 1.63E-03 kg Sb eq.
• pe = 7.18E+00 MJ

Aggregated impacts

$$ \begin{align*}    \mathbf{impact\_ram}(capacity, density) =\ &\mathbf{impact\_ram\_die}(capacity, density) \    &+ \mathbf{impact\_ram\_transportation} \ &+ \mathbf{impact\_ram\_pcb} \ &+ \mathbf{impact\_ram\_gold} \ \end{align*} $$

Source: Green Cloud Computing

For the GPU memory part we can take the impacts of the memory die and transportation. The PCB part is already done above and the gold part can be inferred from the size of the connector (next step).

$$ \begin{align*} \mathbf{GPU}_{\text{manufacture memory chip}}(capacity, density) =\ &\mathbf{impact\_ram\_die}(capacity, density) \ &+ \mathbf{impact\_ram\_transportation} \ \end{align*} $$

[samuelrince]

Interesting observation, we clearly don't have the same values concerning the PCB manufacturing for RAM modules in Green Cloud Computing compared to other studies above.

	Green Cloud Computing	Liu et al., 2014	Ozkan et al., 2018	Nassajfar et al., 2021
GWP (kgCO2eq./m2)	422	39.2	18.6	34.8
ADP (kgSbeq./m2)	1.49e-2	NA	1.71e-3	NA
PE (MJ/m2)	4937	NA	NA	NA

I guess the assumption of a 4-layer PCB is too light for RAM modules and thus GPU board as well? We also need to check where Green Cloud Computing values come from.

[samuelrince]

Concerning the amount of gold in the connector, I think we can estimate based on a comparison of RAM DDR4 connector from Green Cloud Computing and PCIe 4.0 connectors.

DDR4 connector

Specifications:

• 288 pins (144 pins on each side)
• 29.35 mg of gold (from Green Cloud Computing)
• (mean) pin dimensions: 2.15 mm [height] x 0.6 mm [width] (estimated, see below)
• (mean) pin area: 1.29 mm2 (estimated, see below)

Pin area estimation

DDR4 RAM modules have pins of different height, but constant width. Using the schematics from Micron we can get the following dimensions :

• Big pins: 2.4 mm [height] x 0.6 mm [width]
• Small pins: 1.9 mm [height] x 0.6 mm [width]

A small portion of the pins also have intermediate heights between 1.9 and 2.4 mm. I assume that we have 50/50 big pins and small pins. This is an upper bound estimation, there is a little more of small pins compared to big pins. So, the average pin dimensions are 2.15 mm [height] x 0.6 mm [width].

Thus, the average pin area is 2.15 x 0.6 = 1.29 mm2

Density of gold

Total area of pins: 288 * 1.29 = 371.52 mm2 Density of gold: 29.35 / 371.52 ~= 0.07899 mg Au / mm2

PCIe connector

Specifications:

Connector	Number of pins
PCIe x1	36
PCIe x4	64
PCIe x8	98
PCIe x16	164

Today, the majority of GPUs use PCIe x16, and smaller ones use PCIe x8.

From the specs, we can deduce the following characteristics:

• pin dimension: 4.20 mm [height] x 0.70 mm [width]
• pin area: 2.94 mm2

Some pins have a smaller height, but we will not consider it. So, we will get an upper bound estimation.

Amount of gold

From the previous estimations, we can compute the amount of gold for PCIe connectors based on the size of the pins.

Connector	Number of pins	Amount of gold (mg)
PCIe x1	36	8.36
PCIe x4	64	14.86
PCIe x8	98	22.76
PCIe x16	164	38.09

Manufacturing impacts

Based on the impacts reported for DDR4 RAM in Green Cloud Computing, we can estimate them for a PCIe connector.

Connector	Number of pins	Amount of gold (mg)	GWP manufacturing (kg CO2eq.)	ADP manufacturing (kg Sb eq.)	PE manufacturing (MJ)
PCIe x1	36	8.36	1.13e-1	4.64e-4	2.05
PCIe x4	64	14.86	2.35e-1	8.25e-3	3.64
PCIe x8	98	22.76	3.60e-1	1.26e-3	5.57
PCIe x16	164	38.09	6.02e-1	2.12e-3	9.32

[da-ekchajzer]

Nice work ! Thanks for given that mutch detail. As far as I understand, you got all the piece of the GPU puzzle ?

Have you been able to compute it for some GPU ? I would be interested to see and to share it with some “experts”.

[samuelrince]

Thanks @da-ekchajzer I'll make a complete summary and compute for some GPUs this week!

[samuelrince]

Summary of GPU manufacturing impacts

---

Edits:

• Using average memory density from Pirson & Bol 2021 (see comment) ✅
• Corrections on gold quantity of DDR4 and PCIe connectors (see comment) ✅

---

Compute chip

Scope: Die + Transportation

Hypotheses and limitations:

• Wafer substrate production
• Front-end process (FEOL)
• Back-end process (BEOL)
• Transportation
  • From wafer substrate production to front-end process (10,000 km by airplane)
  • From front-end process to back-end process (10,000 km by airplane)
• ⚠️ 14 nm process

$$ \mathbf{GPU}_{\text{manufacture compute chip}}(die\_size) = die\_size * \mathbf{IMP\_GPU\_COMP\_DIE} + \mathbf{IMP\_GPU\_COMP\_DIE\_TRANSPORT} $$

Memory chips

Scope: Die + Transportation

Hypotheses and limitations:

• Wafer substrate production
• Front-end process (FEOL)
• Back-end process (BEOL)
• Transportation
  • From wafer substrate production to front-end process (10,000 km by airplane)
  • From front-end process to back-end process (10,000 km by airplane)
• ⚠️ 20 nm process

$$ \mathbf{GPU}_{\text{manufacture memory chips}}(capacity, density) = \frac{capacity}{density} * \mathbf{IMP\_GPU\_MEM\_DIE} + \mathbf{IMP\_GPU\_MEM\_DIE\_TRANSPORT} $$

Board and other

Scope: PCB + PCIe connector + Heat Sink

Hypotheses and limitations:

• PCIe connector amount of gold is estimated from DDR4 connectors model.
• ⚠️ PCB ?? --> TODO
• ⚠️ Heat Sink ?? --> TODO

$$ \mathbf{GPU}_{\text{manufacture board}}(pcb\_area) = pcb\_area * \mathbf{IMP\_GPU\_PCB} + \mathbf{IMP\_GPU\_PCIE\_X16}^\dagger + \mathbf{IMP\_GPU\_HEAT\_SINK} $$

$\dagger$ we can also consider PCIe x8 connectors for smaller GPUs.

Impact factors

Constant	Impact	Value	Unit
IMP_GPU_COMP_DIE	GWP	1.97E-02	kg CO2eq. / mm2
IMP_GPU_COMP_DIE	ADP	5.87E-09	kg Sbeq. / mm2
IMP_GPU_COMP_DIE	PE	2.65E-01	MJ / mm2
IMP_GPU_COMP_DIE_TRANSPORT	GWP	3.45E-01	kg CO2eq.
IMP_GPU_COMP_DIE_TRANSPORT	ADP	4.33E-08	kg Sbeq.
IMP_GPU_COMP_DIE_TRANSPORT	PE	5.33E+00	MJ
IMP_GPU_MEM_DIE	GWP	2.20E-02	kg CO2eq. / mm2
IMP_GPU_MEM_DIE	ADP	6.30E-07	kg Sbeq. / mm2
IMP_GPU_MEM_DIE	PE	2.73E-01	MJ / mm2
IMP_GPU_MEM_DIE_TRANSPORT	GWP	2.99E+00	kg CO2eq.
IMP_GPU_MEM_DIE_TRANSPORT	ADP	3.75E-07	kg Sbeq.
IMP_GPU_MEM_DIE_TRANSPORT	PE	4.61E+01	MJ
IMP_GPU_PCB	GWP	4.22E-04	kg CO2eq. / mm2
IMP_GPU_PCB	ADP	1.49E-08	kg Sbeq. / mm2
IMP_GPU_PCB	PE	4.94E-03	MJ / mm2
IMP_GPU_PCIE_X16	GWP	2.95E-01	kg CO2eq.
IMP_GPU_PCIE_X16	ADP	1.03E-03	kg Sbeq.
IMP_GPU_PCIE_X16	PE	4.56	MJ
IMP_GPU_PCIE_X8	GWP	1.76E-01	kg CO2eq.
IMP_GPU_PCIE_X8	ADP	6.18E-04	kg Sbeq.
IMP_GPU_PCIE_X8	PE	2.72	MJ
IMP_GPU_HEAT_SINK	GWP	3.12E+00	kg CO2eq.
IMP_GPU_HEAT_SINK	ADP	5.19E-04	kg Sbeq.
IMP_GPU_HEAT_SINK	PE	6.33E+01	MJ

Discussions

• Modern GPUs use a smaller process size for the compute chip (e.g. NVIDIA 40 series use 5 nm process size)
• We assume no difference between DDRx and GDDRx memory chip. The latest has a higher clock speed and bandwidth.
• We assume no difference between GDDR4, GDDR5 and GDDR6.
• We don't know the process size of memory chips.
• We don't know how the heat sink impact scales.
• We took PCB impacts from the Green Cloud Computing study instead of Liu et al. (2014), Ozkan et al. (2018), Nassajfar et al. (2021). The 3 latest studies focus on 4-layer PCB.
• We guesstimated the amount of gold on a PCIe connector from DDR4 connector modeling by computing the mean area of a pin.
• We ignored the impacts of the power transformation / delivery.
• We ignored SXM socket for HPC use case.

Examples

NVIDIA GeForce RTX 4090

Characteristics (from techpowerup)

• die_size = 609 mm2
• memory_capacity = 24 GB
• PCIe x16 connector
• PCB area = 304 x 137 = 32,528 mm2 (⚠️ ISSUE WITH PCB AREA)
• memory_density = 1.625E-02 GB/mm2 (⚠️ from Pirson & Bol 2021)

Impacts

Compute chip

Impact	Formula	Result	Unit
GWP	609 * 1.97E-02 + 3.45E-01	1.23E+01	kg CO2eq.
ADP	609 * 5.87E-09 + 4.33E-08	3.62E-06	kg Sbeq.
PE	609 * 2.65E-01 + 5.33	1.67E+02	MJ

Memory chips

Impact	Formula	Result	Unit
GWP	(24 / 1.625E-02) * 2.20E-02 + 2.99	3.55E+01	kg CO2eq.
ADP	(24 / 1.625E-02) * 6.30E-07 + 3.75E-07	9.31E-04	kg Sbeq.
PE	(24 / 1.625E-02) * 2.73E-01 + 4.61E+01	4.49E+02	MJ

Board

Impact	Formula	Result	Unit
GWP	32528 * 4.22E-04 + 2.95E-01 + 3.12	1.71E+01	kg CO2eq.
ADP	32528 * 1.49E-08 + 1.03E-03 + 5.19E-04	2.03E-03	kg Sbeq.
PE	32528 * 4.94E-03 + 4.56 + 6.33E+01	2.29E+02	MJ

Total

Impact	Formula	Result	Unit
GWP	1.23E+01 + 3.55E+01 + 1.71E+01	64.9	kg CO2eq.
ADP	3.62E-06 + 9.31E-04 + 2.03E-03	2.96E-3	kg Sbeq.
PE	1.67E+02 + 4.49E+02 + 2.29E+02	845	MJ

NVIDIA A100 80GB

Characteristics (from techpowerup)

• die_size = 826 mm2
• memory_capacity = 80 GB
• PCIe x16 connector
• PCB area = 267 x 111 = 29,637 mm2
• memory_density = 1.625E-02 GB/mm2 (⚠️ from the Pirson & Bol 2021)

Impacts

Compute chip

Impact	Formula	Result	Unit
GWP	826 * 1.97E-02 + 3.45E-01	1.66E+01	kg CO2eq.
ADP	826 * 5.87E-09 + 4.33E-08	4.89E-06	kg Sbeq.
PE	826 * 2.65E-01 + 5.33	2.24E+02	MJ

Memory chips

Impact	Formula	Result	Unit
GWP	(80 / 1.625E-02) * 2.20E-02 + 2.99	1.11E+02	kg CO2eq.
ADP	(80 / 1.625E-02) * 6.30E-07 + 3.75E-07	3.10E-03	kg Sbeq.
PE	(80 / 1.625E-02) * 2.73E-01 + 4.61E+01	1.39E+03	MJ

Board

Impact	Formula	Result	Unit
GWP	29637 * 4.22E-04 + 2.95E-01 + 3.12	1.59E+01	kg CO2eq.
ADP	29637 * 1.49E-08 + 1.03E-03 + 5.19E-04	1.99E-03	kg Sbeq.
PE	29637 * 4.94E-03 + 4.56 + 6.33E+01	2.14E+02	MJ

Total

Impact	Formula	Result	Unit
GWP	1.66E+01 + 1.11E+02 + 1.59E+01	143	kg CO2eq.
ADP	4.89E-06 + 3.10E-03 + 1.99E-03	5.09E-3	kg Sbeq.
PE	2.24E+02 + 1.39E+03 + 2.14E+02	1828	MJ

[samuelrince]

Follow-up meeting with UCL researchers

• Data for IC with a technology node < 14 nm should be available in the following weeks/months.
• Notation: back-end process ≠ BEOL (BEOL is part of the front-end process).
• Total impacts seem low (more than double GWP for A100 GPU).
• The 10x factor for PCB between GCC and other studies cannot be explained only by the number of layers. We need to investigate where that number is coming from. Between 1-layer and 16-layer impact is x5 max.
• We probably cannot ignore the impact of the power supply (eco-toxicity).
• For SXM we will need an LCA; otherwise it seems very complicated.
• Impact factor for IC (GWP 2kg/cm2) is most likely a lower bound.
• Notation: use technology node instead of process size.
• Notation: use die area instead of die size.
• We will need at some point to consider the casing of GPUs, that can have an impact as well (start from the weight?)
• Definitely crypto mining ASICs ≠ GPU
• Using memory die are is better than guessing it using the density. But, we need to check if we can access that information.
• We also ignore nvlink connectors

[samuelrince]

One quick explanation on why the impacts are low (especially for the memory part) is the calculation of density. In the old (pre-v1) API version, we use the value that maximizes the impact. The density is thus 0.625 GB/cm2 compared to the value taken here of 1.875 GB/cm2. The first value corresponds to a Samsung DRAM with a technology node of 30 nm (Green Cloud Computing). 30 nm technology node for DRAM seems to be pre 2014 value. The second value is the average for 20 nm.

Data from Green Cloud Computing (⚠️ pay attention to units in this table):

I feel like for the case of GPUs and especially recent ones like the NVIDIA GeForce RTX 4090 and NVIDIA A100 80 GB from above, it is fair to take the value from 20 nm technology node instead of the "old" 30 nm, even though it reduces the impact.

We can also consider from Pirson & Bol 2021 a calculated average over ~12 years of data from 2010 to 2022 density for DRAM of 1.625 GB/cm2.

Here are the different values of memory chips impacts of an NVIDIA A100 80 GB with difference hypotheses:

	RAM module (API pre-v1)	Density of 0.625 GB/cm2	Density of 1.625 GB/cm2	Density of 1.875 GB/cm2
GWP (kg CO2eq.)	290	284.6	111.3	96.9
ADP (kg Sbeq.)	9.80E-03	8.06E-03	3.11E-03	2.69E-03
PE (MJ)	3600	3540	1390	1211

Do you have an opinion on this @ThibaultPirson @blubrom @da-ekchajzer ?

[samuelrince]

Corrections on gold quantity of DDR4 and PCIe connectors

Looking back at the Green Cloud Computing study hypotheses for gold quantity estimation on a DDR4 connector, I have noticed some issues both in the study and in our estimations of pin area above.

Estimation of the gold area in GCC study

From this table, we have an estimation of the pin area (thus area of gold) on the connector of 760 mm2. I have not found the precise calculation in the study, but I believe it is done the following way:

1. Compute the total width of the connector populated with pins: 56.10 + 64.5 = 120.6 mm

Schema from Micron

2. Multiply by the "maximum height of a pin": 3.15 mm

3. Compute the total area of the connector (on both sides of the module): 120.6 x 3.15 x 2 = 759.78 mm2 ~= 760 mm2

⚠️ This is wrong because it ignores that the pins are separated.

Manual estimation of the pin size (2nd try)

Using another data sheet from Samsung, we have the precise quotations of the pin dimensions.

The pin width is still 0.60 mm, but the height ranges from 2.25 to 1.75 mm. We can repeat previous calculations to estimate the total area of pins.

• Average pin height: (2.25 + 1.75) / 2 = 2.00 mm
• Average pin area: 2.00 * 0.60 = 1.20 mm2
• Estimation of total area: 1.20 * 288 = 345.6 mm2

⚠️ Previously we've estimated ~371.52 mm2~ instead of 345.6 mm2

Quantity of gold

Using the density of gold at 19.32 g/cm3 and with the hypothesis that the gold layer thickness is 2 µm, we can re-estimate the quantity of gold needed for a connector based on the total area of the pins.

• Quantity of gold: 3.456 * 0.0002 * 19.32 = 13.35 mg

⚠️ Compared to GCC study (29.35 mg), that is around a factor x2 error.

Update on PCIe

Recall pin size/area from the specs:

• pin dimension: 4.20 mm [height] x 0.70 mm [width]
• pin area: 2.94 mm2

We can update accordingly the quantity of gold and impact factors:

Connector	Number of pins	Amount of gold (mg)	GWP manufacturing (kg CO2eq.)	ADP manufacturing (kg Sbeq.)	MJ manufacturing (PE)
PCIe x1	36	4.09	6.45E-02	2.27E-04	1.00
PCIe x4	64	7.27	1.15E-01	4.04E-04	1.78
PCIe x8	98	11.13	1.76E-01	6.18E-04	2.72
PCIe x16	164	18.63	2.95E-01	1.03E-03	4.56

[samuelrince]

🔴 Draft

Corrections on die manufacturing impacts

Another feedback from UCL researchers is that our impact factor for die manufacturing is probably a lower band compared to other studies. A comparative analysis in Pirson et al. 2023 draw the following graphs:

Primary Energy: (in red the current value we are using)

Global Warming Potential: (in red the current value we are using)

Data from imec.netzero

Example of data we can get from imec.netzero [public] database for a A100-like GPU die:

Parameters:

• Location: Industry Average
• Die dimensions: 25 mm [x] ; 33 mm [y] = 825 mm2
• Die yield: Murphy set at 0.1 defect/cm2 (see also die yield calculator and ‘Better Yield on 5nm than 7nm’: TSMC Update on Defect Rates for N5)
• Abatement model: IPCC Tier 2C with combustion
• Electricity carbon intensity: By geographical location