Static analyzer for standard an ultra circuits

[Rumata888]

A mechanism that treats the whole circuit before finalization (in case of ultra) as a graph with additional information and looks at the following properties:

1. How many independent subgraphs (real variables being vertices) there are
2. Whether there are any unexpected variables only present in 1 gate (apart from known cases this signals and underconstrained circuit)

### Tasks
- [x] Create Initial implementation of static analyzer with lookup, arithmetic, sorted, elliptic gates taken care of
- [x] Create PR patch for the discovered issue
- [ ] Finalize and clean up PR with initial implementation and with AES and SHA256 tests
- [ ] Create tests for blake
- [ ] Extend mechanism to Auxiliary and Poseidon gates
- [ ] Create tests for cycle group