Andrew Nolte
Andrew Nolte
This is allowable through vpi, but not with the current simulator implementation. The simulator change is in #3608. A handle.py change is needed in order to interact with structs while...
This commit https://github.com/cocotb/cocotb/commit/a59fba89fe177d9d0d2532238a55f85a0a18e4f1 breaks a lot of code I think str(dut.myhandle) should be removed, because the cast does something that's sort of ambiguous- it seems like it might interpret the...
I think it would be great to have inlay hints similar to the clangd extension. Here are some ideas for where they could be used: - parameter values (would need...
I think it was be nice to customize the project descriptor format, rather than just sticking to the standard ones like EDAM and vunit. For example, settings up a configuration...
This one: https://www.amazon.com/gp/product/B091ZT4L78/ Keep getting this, and also a similar message with get_version_tuple. Does this new one just not follow the protocol, or is something wrong with the networking? Update:...
Only print the json for a scope up to this module depth. I'm requesting this because the json files can quickly get way too huge to manage. Also, should the...
Typename tc According to the spec, the last three lines should be ``` enum{A=32'sd0,B=32'sd1,C=32'sd99}A::e$1 A::bit[9:1] struct{bit A;bit B;}top.AB_t$[0:9] ```
The LRM Specifies this in 20.6.1: ``` // source code // $typename would return typedef bit node; // "bit" node [2:0] X; // "bit [2:0]" int signed Y; // "int"...
If the top level has a defaultless parameter, port/param names of submodules are not checked. Test case here: https://github.com/MikePopoloski/slang/pull/987 I'm not sure if this is a feature request or a...
If the top level has a defaultless parameter, port/param names of submodules are not checked. If the parameter bar is given a default, this test passes and it correctly gives...