SDRPlusPlus
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Limited Sampling Rate
Hardware
- SDR: USRP B210 connected locally
Software
- Operating System: Ubuntu 22.04
- SDR++: v1.1.0
Bug Description Even though the maximum supported sampling rate is higher, the maximum Sample Rate in GUI is 16 MHz, both using USRP and SoapySDR driver.
How can I increase the max sampling rate?
Hello , Normally the device promises 56MHZ bandwidth. I have the same problem with the USRP B200mini. I cannot see more than 16mhz bandwidth on the screen.
Not a bug, base clock selection just hasn't been implemented yet. I'll change this to a feature request.
Got it, thanks.
Bandwidth is for the input filter, has nothing to do with available samplerates. As I said in my last response, the reason the samplerate is limited to that value is the baseclock is set to 16MHz. It has to be dynamically adjusted but I have yet to determine an algorithm to select the best options.
My apologies, previous posts were wrong and I deleted them.
Setting the master clock rate manually allows me to view the full bandwidth using the B210mini clone instead of just 16MHz. What effect this may have beyond just watching the waterfall is beyond my level of understanding.
// Set the master clock rate to 56 MHz (or adjust as necessary)
double master_clock_rate = 56e6; // 56 MHz
dev->set_master_clock_rate(master_clock_rate);
double actual_clock_rate = dev->get_master_clock_rate();
if (actual_clock_rate != master_clock_rate) {
flog::warn("Requested clock rate of 56 MHz, but actual clock rate is {0} MHz", actual_clock_rate / 1e6);
}
[INFO] [B200] Setting master clock rate selection to 'automatic'.
[INFO] [B200] Asking for clock rate 16.000000 MHz...
[INFO] [B200] Actually got clock rate 16.000000 MHz.
[16/08/2024 21:50:53.000] [WARN] ConfigManager locked, waiting...
[INFO] [MULTI_USRP] Setting master clock rate selection to 'manual'.
[INFO] [B200] Asking for clock rate 56.000000 MHz...
[INFO] [B200] Actually got clock rate 56.000000 MHz.
Thanks again for your great work!
I want to modify this code you shared below to manually set the master clock rate to 28mhz. But where exactly do I paste it?
// Set the master clock rate to 56 MHz (or adjust as necessary)
double master_clock_rate = 56e6; // 56 MHz
dev->set_master_clock_rate(master_clock_rate);
double actual_clock_rate = dev->get_master_clock_rate();
if (actual_clock_rate != master_clock_rate) {
flog::warn("Requested clock rate of 56 MHz, but actual clock rate is {0} MHz", actual_clock_rate / 1e6);
}
I want to modify this code you shared below to manually set the master clock rate to 28mhz. But where exactly do I paste it?
I added it to source_modules/usrp_source/src/main.cpp on line 139. Again, this is only to allow you to select the higher value, no idea about best use case and performance. here: https://github.com/AlexandreRouma/SDRPlusPlus/blob/3982db73d3f9d27972feaff819fe08e9ec7b4c82/source_modules/usrp_source/src/main.cpp#L139
Hello Alex,
I have my usrp b205 device. Thanks for the code. I experimented with 28mhz, 40mhz, 56mhz. At these bandwidths, the waterfall visually flows smoothly. But when I select a channel in the FM radio band and listen, the sound is intermittent. I guess it doesn't work properly in this way :( did you do a test like this? For example, did you try listening to FM radio with 28mhz or 56 baseclock?
I think AlexandreRouma will solve this when the time comes :) we are waiting patiently.
Hello Alex,
I have my usrp b205 device. Thanks for the code. I experimented with 28mhz, 40mhz, 56mhz. At these bandwidths, the waterfall visually flows smoothly. But when I select a channel in the FM radio band and listen, the sound is intermittent. I guess it doesn't work properly in this way :( did you do a test like this? For example, did you try listening to FM radio with 28mhz or 56 baseclock?
I think AlexandreRouma will solve this when the time comes :) we are waiting patiently.
Mine works great and I have no issues with sound unless I select 56 and get overruns at high bandwidth. I’ve added extra code to populate the full range of samplerate and bandwidth. The only weird thing I see is some aliasing on certain selections.
Hello again Alex, which driver version are you using, can you share the link if possible (files.ettus.com/binaries/uhd/)
Also, if possible, can you share main.cpp with me?
I'm on MacOS 15 arm64 using the UHD that's available via brew. ==> uhd: stable 4.7.0.0 (bottled), HEAD My b210 fpga bin is a custom build by the Chinese seller of the clone. I never got around to finding the differences in the fpga code between the one provided by the seller and the binaries provided directly from USRP. The latter do not work on this device.
Here are my changes. Use at your own risk https://pastebin.com/AMyXs9Ab