fpgaconvnet-hls

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Generating SPLIT and CONCAT layers

2

Hi, I am trying to generate a model with SPLIT and CONCAT layers, and I see that both functions are in the code but are not implemented. https://github.com/AlexMontgomerie/fpgaconvnet-hls/blob/dd28baa781df6e6dfebca3314305da4599816d83/fpgaconvnet/hls/generate/partition.py#L102 https://github.com/AlexMontgomerie/fpgaconvnet-hls/blob/dd28baa781df6e6dfebca3314305da4599816d83/fpgaconvnet/hls/generate/partition.py#L106) This...

fPecc

Fix accompanying changes to the fpgaconvnet-model repository.

MichalPalic

1. Implementation to allow passing `port_width` 2. Implementation to allow passing `DMA_WIDTH` and `DATA_WIDTH` 3. Implementation to reformat `common.hpp` and `common_tb.hpp` header files 4. Fix data overlap issues in `mem_write`...

lgxi24

abdalrahimnaser

Hi, Does it work with Vivado HLS 2020.1? because I am recieving the following issue and wonder whether the HLS version is the problem.

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abdalrahimnaser