Fault Scan chain Verification failed

Hi, While running fault chain command I bumped into an error. Please refer image.

I generated TV with default options. The prompt displays "Scan chain verification failed". I'm confused, which program is being referenced here that requires clock and reset? The netlist generated using yosys contained reset and clock signals. The reset in my design is synchronous(and is the only reset signal). Even with all these errors, .chained file is created in my netlist folder. I'm able to run tap asm command and check the created .bin files. I encountered similar issue while running fault tap command. .jtag file was created but the prompt displayed "Tap port verification failed".

Also, I'm curious to know what would have been the output if both these steps verified successfully.

Regards, Piyush

Jun 30 '21 21:06 PiyushSaini97

That scan chain verification just verifies if the created scan chain works properly. That means it failed. The tap also fails because scan chain verification fails. It doesn't affect the creation of the scan chain itself.

I'll have to test and get back to you on why counter is failing scan chain verification. Thank you for your patience and diligence in reporting bugs. :)

Jul 01 '21 15:07 donn

Not only counter. I tried running universal 8 bit shift register.

Code:

Unfortunately I encountered the same error :(

Jul 01 '21 17:07 PiyushSaini97

@donn I understood the problem. I was using asynchronous reset in both of my designs. For that reason my scan chain verification failed. After changing that my scan chain verified successfully.

However, now I bumped into another error. I ran fault tap and got this