[RCFC] LPC4322 SWD-SGPIO.

[groleo]

Requires #906.

This p-r is replacing the bit-banged SWD implementation with one which uses the lpc4322's SGPIO. Transfer rate reported by IAR is around 380 kB/sec with DAP.nominal_clock @30MHz and SGPIO_CLK@120MHz. Maximum I could get was 420 kB/sec with DAP.nominal_clock @40MHz and SGPIO_CLK @204MHz;

testing in progress.

[groleo]

v2:

• fixed the lpc4322_bl target by defining SWDP_SGPIO per-board (records/board/mimxrt1170_evk_qspi.yaml)
• use DAP_Data.nominal_clock instead of infering it from DAP_Data.clock_delay.

[groleo]

v3:

• fix DAP_Info for debuggers not yet supporting cmsis-dap v2.1.

v2:

• fixed the lpc4322_bl target by defining SWDP_SGPIO per-board (records/board/mimxrt1170_evk_qspi.yaml)
• use DAP_Data.nominal_clock instead of infering it from DAP_Data.clock_delay.

[mathias-arm]

@groleo: Can you put [8774a9e] in a separate PR?

[groleo]

@groleo: Can you put [8774a9e] in a separate PR?

Done

[groleo]

v4: add sequence_read(). proper SGPIO_CLK initialization and setup. add idle_cyles. explicitly set the P1_17 mode so that it's visible it's a Hard-Drive pin (doesn't support slew-rate programming and it's driven @4mA)

[elfmimi]

I'm experimenting reconfiguration of PLL to match required SWD frequency. Based on your code. It can run at SWD clock speed ranging 50MHz down-to 1kHz . https://github.com/elfmimi/DAPLink/tree/lpc4370_sgpio_pll_sequence_fix_if_wip

[elfmimi]

Current status of this pull-request.

• Build the interface firmware from pr's head commit https://github.com/ARMmbed/DAPLink/commit/9f1413746d412631d521b1fcbb1c36c61d182dfd progen generate -p lpc4322_mimxrt1170_evk_qspi_if -t make_gcc_arm -b -o jobs=8
• Install the interface firmware using the bootloader firmware lpc4322_bl Dev board I'm using has different target MCU. But it's OK for testing pyOCD access.
• Results
  • pyOCD can connect to the onboard target LPC43S67 but only when frequency setting is high enough. python -mpyocd cmd -t cortex_m -f 3000000
  • pyOCD can connect to external targets. for example RaspberryPi Pico - RP2040 , but with the same frequency constraint. python -mpyocd cmd -t rp2040 -f 3000000
  • pyOCD can not connect to some external targets. for example nRF52840.

[elfmimi]

I want to see this going forward.

[groleo]

Hi @elfmimi ,

what testing infra do you use?

I've more or less used the on-board debug probe (on the rt1170-evk) and many reboot/flash-daplink cycles but I would benefit from some sort of logging/output.

I also have a OM13070 (which has a LPC4322) if this can be used for test setup.

thx

[elfmimi]

Oh, I used OM13084 (interface: LPC4322 , target: LPC43S67) . OM13070 (interface LPC4322 , target: LPC4337) should work just fine as well.

In case of OM13070 , LPCX4337_V3_SCHEMATIC_REVA3 , you can access SWD pins of LPC4322 through these test points. Z11 = SWCLK Z12 = GND Z13 = SWDIO

For logging/output Segger RTT might be the best option.

[elfmimi]

Please have a look at this branch for how to do RTT. @groleo https://github.com/elfmimi/DAPLink/tree/pull907-fix-and-rtt

After executing the above code, attach with pyocd to get the log. pyocd rtt -t cortex-m -f 12000000 -a 0x10000000 -s 0x8000

[elfmimi]

You don't even need soldering to connect to SWD pins.

[groleo]

Cool. And I should stick the SWD wires in a UART-over-USB ?

[elfmimi]

Yes, it's cool! No. SWD is SWD. bring in another CMSIS-DAP adapter. RTT is a software solution which establishes logical pipe over SWD connection.

[groleo]

which probe should I get ? Is the picoprobe ok ?

[elfmimi]

picoprobe ~may be~ is confirmed okay. If you have RaspberryPi Pico to spare , try rust-dap . pre-compiled binaries here. https://github.com/elfmimi/rust-dap/releases/tag/preview-0.1

[groleo]

that "may be ok" sounds worrisome (i'd like to avoid debugging the debugger).

Do you have a recommendation that's sure to work (or you use yourself) ? thx

[elfmimi]

I suppose we should move this talk to daplink channel of pyOCD slack. https://pyocd.slack.com/archives/C02GTJPENEN