[BUG] Neon vector shift left and widen intrinsic variants with n == bit-width

[namniav]

Describe the bug

From https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-shift-left-and-widen, each neon vector shift left and widen intrinsic has a variant with n == bit width.

For example:

Intrinsic	Argument preparation
int16x8_t vshll_n_s8(int8x8_t a, const int n)	0 <= n <= 7
int16x8_t vshll_n_s8(int8x8_t a, const int n)	n == 8

Both link to the same developer.arm.com page for vshll_n_s8 and the documented argument preparation there is n -> minimum: 0; maximum: 7.

What is the use of the second variant? Or is it a mistake?

[vhscampos]

Thanks for the bug report.

This is indeed a bug. developer.arm.com is missing the second variant, which is translated into the SHLL instruction (instead of SSHLL).