Cortex M Level-1 cache functions Enhancement of the documentation

[FerdinandEn]

Current content of the help (CMSIS 5.9.0)

__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr(volatile void * addr,int32_t dsize ) D-Cache Invalidate by address. Parameters [in] addr address (aligned to 32-byte boundary) [in] dsize size of memory block (in number of bytes) The function invalidates a memory block of size dsize [bytes] starting at address address. The address is aligned to 32-byte boundary.

Doxygen function comment

/**
  \brief   D-Cache Invalidate by address
  \details Invalidates D-Cache for the given address.
           D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
           D-Cache memory blocks which are part of given address + given size are invalidated.
  \param[in]   addr    address
  \param[in]   dsize   size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)

In the Doxygen comment, another condition for using the cache function is that the size of the block must be a multiple of its 32 bytes. I became aware of the problem when I chose a variable too small to be the destination of a DMA. This resulted in unintentionally changing contents of neighboring variables. The cache function also works correctly when the dsize is smaller than n 32 bytes. However, n 32 bytes are updated. The same problem occurs with the SCB_CleanDCache_by_Addr() statement.

My suggestion is to point out in the help that the cache instruction always updates a block of n 32 bytes.

A spelling mistake in the help is also that the word address is written twice in a row. See above

[JonatanAntoni]

Hi @FerdinandEn,

Thanks for pointing this out. Documentation is always an issue and if you like to update the description this is more than appreciated.

Please feel free to raise a PR with your suggestion.

Thank you very much, Jonatan