Basic-SIMD-Processor-Verilog-Tutorial
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zslwyuan
help needed for runing simulation in Vivado 2020.1
Sir, i'm new to verilog and trying to explore and learn. I found SIMD processors interesting and so took it as project. I have took the source codes made available here and pasted it as it is in Xilin's Vidvado 2020.1 version. now ideally i though it will working without problems.
But, i have encounter with ERRORS,
in General Section: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Ren.Ps/Documents/VHDL/SIMD/SIMD.sim/sim_1/behav/xsim/elaborate.log' file for more information.
[Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
In Simulation Section: [XSIM 43-3230] Could not open sdf file "CPUtop.mapped.sdf". [XSIM 43-3915] Encountered a fatal error. Cannot continue. Exiting...
i'm not able to resolve this from weeks now. can you or anyone help me to resolve and get the testebench waveform. plz.
Sorry for replying late but I am not sure about your issue. Maybe there is some useful information in "C:/Users/Ren.Ps/Documents/VHDL/SIMD/SIMD.sim/sim_1/behav/xsim/elaborate.log"? For your second issue, I guess that the SDF file "CPUtop.mapped.sdf" is not supposed to be imported in our simulation unless you want to check energy consumption of the circuit.
Oh,I had the same problems when I ran simulation.And it`s also in Xilinx Vivado 2020.1 version.
Oh,I had the same problems when I ran simulation.And it`s also in Xilinx Vivado 2020.1 version.
Hi @jimik7 , can you provide the log file so I can have a close check? Thanks