Basic-SIMD-Processor-Verilog-Tutorial
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Dependency between adder blocks.
Hi, as you mentioned, each adder block forwards carry bit between other adders. But there is some dependency in here that each adder block waits for the carry to arrive from its previous block. I think would be carry look-aheader adder design to reduce propagation delay instead of current solution.

Hi @eminghuliev ,
Thanks a lot for your suggestion! Yes! You are right!
Using look-ahead adder will definitely improve the performance! Just need to carefully handle the compatibility among different input operand bitwidth. ^_^
Cheer up!