Zapta

Will the -g2012 work also with existing verilog projects or is it something that we need to control on/off? On Tue, Dec 17, 2024 at 12:14 PM Guido Sanchez ***@***.***>...

Does this mean that .sv and .v files can't be mixed in the same project? I am working now on making apio.ini a required file so we can add there...

Hi @gmsanchez, the two policy items you suggested sound good, safe, and feasible.

Hi @gmsanchez, I was able to reproduce your success but ``apio graph`` still fails. Can you take a look? Attached is my sv proj. [and-gate.zip](https://github.com/user-attachments/files/18174759/and-gate.zip) ``` /projects/apio-dev/repo/test-examples/TB/edu-ciaa-fpga/and-gate$ apio graph Setting...

Hi @gmsanchez, when I use the slang options I get graph failues with a few of the apio examples. For example, the one below ``upduino31/blinky``. BTW, I think that 'SB_RGBA_DRV'...

Thanks! It helps a lot. On Wed, Dec 18, 2024 at 11:29 AM Guido Sanchez ***@***.***> wrote: > I have asked about that issue here: YosysHQ/oss-cad-suite-build#133 > > > In...

FYI, https://stackoverflow.com/questions/79292059/does-the-systemverilog-standard-allows-mixing-with-verilog-files On Wed, Dec 18, 2024 at 11:53 AM Tal Dayan ***@***.***> wrote: > Thanks! It helps a lot. > > On Wed, Dec 18, 2024 at 11:29 AM...

I am not an expert but since you didn't get yet an answer, here is my 2c. APIO is a user friendly wrapper around yosys and the issue you mentioned...

@jasonsbeer, this issue seems to belong to yosys. Please file it there. Link above. As a layman, name change may affect the internal ordering of networks and nodes and affect...

Let's see if we can figure out the apio graph issue, If not we can block it for projects with .sv with a proper error message.