sv2v-generated Verilog code triggers Yosys error: "Insufficient number of array indices for entries"

[mmxsrup]

I am converting SystemVerilog code from the SoomRV commit e680967, to Verilog using sv2v. After converting, I attempted to load the generated core.v file using Yosys, but encountered the following error:

ERROR: Insufficient number of array indices for entries.

Steps to reproduce:

1. Clone the SoomRV repository and checkout commit e680967:

git clone https://github.com/mathis-s/SoomRV.git
cd SoomRV
git checkout e680967

2. Modify the Makefile by adding the following lines:

diff --git a/Makefile b/Makefile
index 5ff0dca..e206a46 100644
--- a/Makefile
+++ b/Makefile
@@ -144,6 +144,10 @@ $(SLANG_HEADER_OUTPUT): src/Config.sv src/Include.sv
                echo "warning: Could not find slang-reflect, continuing without. Cosim will not be updated if parameters change.";\
        fi

+.PHONY: sv2v
+sv2v: $(SRC_FILES)
+	sv2v -w /tmp/core.v $(SRC_FILES)
+
 .PHONY: clean
 clean:
 	$(RM) -r obj_dir

3. Run sv2v to generate core.v:

make sv2v

4. Try to load the resulting Verilog file with Yosys:

yosys

Then execute in the Yosys shell:

read_verilog -sv /tmp/core.v

Observed result:

Yosys reports the following error:

/tmp/core.v:3951: ERROR: Insufficient number of array indices for entries.

Additional Information:

I have attached the generated core.v file for reference.

The code around line 3951 in core.v is as follows:

	function automatic [(($clog2(NUM_ENTRIES) + 1) >= 0 ? $clog2(NUM_ENTRIES) + 2 : 1 - ($clog2(NUM_ENTRIES) + 1)) - 1:0] sv2v_cast_16026;
		input reg [(($clog2(NUM_ENTRIES) + 1) >= 0 ? $clog2(NUM_ENTRIES) + 2 : 1 - ($clog2(NUM_ENTRIES) + 1)) - 1:0] inp;
		sv2v_cast_16026 = inp;
	endfunction
	always @(deqIndex or IN_SQ_done or deqIndex or baseIndex[0+:$clog2(NUM_ENTRIES)] or baseIndex[$clog2(NUM_ENTRIES)+:TAG_SIZE] or IN_comLoadSqN or deqIndex or entries or deqIndex or entries or deqIndex or entries or ltIssue or deqIndex or ltIssue or ltIssue or entries or entries or entries or _sv2v_0 or IN_memc[62]) begin : sv2v_autoblock_9 // <------- 3951
		reg memcNotBusy;
		memcNotBusy = !IN_memc[62];
		if (_sv2v_0)
			;
		begin : sv2v_autoblock_10
			integer h;
			for (h = 0; h < NUM_AGUS; h = h + 1)
				begin : sv2v_autoblock_11
					reg [NUM_ENTRIES - 1:0] issueCandidates;
					issueCandidates = 0;
					ltIssue[h] = sv2v_cast_16026({sv2v_cast_D4EE8(1'sbx), 2'bx0});
					begin : sv2v_autoblock_12
						integer i;
						for (i = 0; i < NUM_ENTRIES; i = i + 1)
							issueCandidates[i] = (entries[i][0] && !entries[i][2]) && !entries[i][3];
					end
					begin : sv2v_autoblock_13
						integer i;
						for (i = 0; i < h; i = i + 1)
							if (ltIssue[i][0])
								issueCandidates[ltIssue[i][$clog2(NUM_ENTRIES) + 1-:(($clog2(NUM_ENTRIES) + 1) >= 2 ? $clog2(NUM_ENTRIES) + 0 : 3 - ($clog2(NUM_ENTRIES) + 1))]] = 0;
					end
					begin : sv2v_autoblock_14
						integer i;
						for (i = 0; i < NUM_ENTRIES; i = i + 1)
							begin : sv2v_autoblock_15
								reg [$clog2(NUM_ENTRIES) - 1:0] idx;
								idx = i[$clog2(NUM_ENTRIES) - 1:0] + deqIndex;
								if (issueCandidates[idx] && !ltIssue[h][0]) begin
									ltIssue[h][1] = 0;
									ltIssue[h][0] = 1;
									ltIssue[h][$clog2(NUM_ENTRIES) + 1-:(($clog2(NUM_ENTRIES) + 1) >= 2 ? $clog2(NUM_ENTRIES) + 0 : 3 - ($clog2(NUM_ENTRIES) + 1))] = idx[$clog2(NUM_ENTRIES) - 1:0];
								end
							end
					end
					if (((((h == 0) && entries[deqIndex][0]) && !entries[deqIndex][2]) && entries[deqIndex][3]) && ((IN_comLoadSqN == GetLoadSqN(deqIndex)) && IN_SQ_done)) begin
						ltIssue[h][1] = 0;
						ltIssue[h][0] = 1;
						ltIssue[h][$clog2(NUM_ENTRIES) + 1-:(($clog2(NUM_ENTRIES) + 1) >= 2 ? $clog2(NUM_ENTRIES) + 0 : 3 - ($clog2(NUM_ENTRIES) + 1))] = deqIndex;
					end
				end
		end
	end

The corresponding original SystemVerilog code is located here.

I suspect this might be due to an sv2v conversion issue or incompatibility with Yosys parsing. Any assistance or advice on how to resolve this would be greatly appreciated.