Jake Taylor

cheers, let me know if something is strange/unclear!

I believe [this](https://github.com/rust-lang/rust/issues/76560) will also be required for this use case in order to be able to calculate bit widths for combined `Signal`s - eg. `a * b` will produce...

> Is it possible to use https://docs.rs/typenum instead before the stablization of generic_const_exprs? Very interesting, it looks like this may have what we need. I’ll do some evaluation work and...

Heh, I didn't know clippy had lints for this, that's great! I haven't run it locally yet, but I suspect this is due to using `Signal` references as keys. In...

Re perf, until #23 is solved/changed/landed, there may be significant changes in the Verilog generation code (see [this issue comment](https://github.com/yupferris/kaze/issues/14#issuecomment-906124095) for a mini-status-update on that). However, if you'd still like...

Something like: ```rust let c = Context::new(); let empty = c.module("Empty"); // no inputs/outputs // Both sim and verilog gen should fail when validating the module sim::generate(empty, sim::GenerationOptions::default(), std::io::stdout())?; verilog::generate(empty,...

Finally getting a chance to look at this, and first off, let me say this is great work, and I'm super pleased to see it! We've been wanting to build...

FYI, #72 (which superceded #52) was just landed/merged.

re the Invoke-WebRequest cmdlet for Windows builds, I too noticed that this was a bit flaky - however, you can use the "re-run incomplete" button in the appveyor UI to...

As for old projects, it may be possible to provide a VST2 -> VST3 conversion path, though this would have to be per-DAW. It's likely that the most pragmatic option...