unicorn

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Segfault while mem_writing inside a mem read hook.

5

Hello, First, thanks for the great tool. I wanted to do some kind of man-in-the-middle on memory accesses. But under certain conditions, using uc_mem_write() inside a mem read hook leads...

futhewo

Enabling MMU causes unrecoverable prefetch abort interrupt on UC_CPU_ARM_926

2

I am trying to emulate system software that enables the MMU and D-cache feature of the ARM926EJ-S processor, however when the instruction to enable this is executed, an instruction fetch...

InvoxiPlayGames

[RFC] Restore py2 compatibility by using 2 files

8

This should bring back Python2 compatibility. Q: Does this affect the current Python3 code using Unicorn2? In theory, no. Q: Does this affect the previous Python2 code using Unicorn1? In...

wtdcode

Ignore page_collection_lock

5

Unicorn is already ignoring page locks, so we also don't need to manage the page collection and its tree objects. It helps us to avoid redundant object allocations and speed...

tunz

Add new cargo release for unicorn2

2

Since the `ffi` is exposed on dev branch now, and the `set_cpu_model` enums have been added (among others), can the maintainers push a new cargo `2.0.x` release? thanks

lockbox

Let pip deal with whl filename

12

I tried to create a whl from an alpine linux docker image of the latest Unicorn release and the whl build works fine but due to that `if` statement removed...

Antelox

bet4it

No apparent binding / mechanism for raising hardware interrupts in the emulation.

3

I say "apparent" because Qiling must have a way to do this, but I haven't been able to to work out how. QEMU itself has the machinery, but it doesn't...

John-Titor

UC_ERR_INSN_INVALID while emulating the mrc arm32 instruction.

3

Although, there is already an implementation for the mrc instruction in this [commit](https://github.com/unicorn-engine/unicorn/commit/8bc1489210f24b2b64b505af048a10da0b25fbea) The following code doesn't work, although capstone is able to disassemble that instuction ``` #!/usr/bin/env python from...

F1o0T

Missing something risc-v delegable_ints env->miclaim

3

Hello, I appear to be missing something. I am trying to use Unicorn for a risc-v project and trying to set the mip register which calls qemu/target/riscv/csr.c and get to...

mischievous