Add SRAM-like Mem generators to ChiselUtil

[sdtwigg]

A common issue with users is that Mem their designs are not being properly inferred to have the right ports. (For example, not merging related R and W ports into a R/W port, not being sequentially read, etc.)

Adding Mem wrapper to ChiselUtil where you specify how many R, W, and R/W ports you desire would resolve this issue. Also, this wrapper could be tested with the test infrastructure to ensure changes to Mem are actually being tested and user code is backwards-compatible with inference changes.