Feature : verilog's signals parameter ex : (* KEEP = "TRUE" *)

[Dolu1990]

Hi, It would be useful to alow to set custom parameter (verilog backend) to signals and ram. For example with xilinx FPGA : (* KEEP = "TRUE" *) reg [10:0] myRegister;

Use case : Last day i had to increase FMax of a design, so, i have add some flip flop to pipeline the design but the hardware synthesis remove it => need KEEP attribut to force to keep it.

Use case : Force to synthesis RAM into distributed or block (* RAM_STYLE="{AUTO | BLOCK | DISTRIBUTED}" *)

Are you interrested in ?

[shunshou]

Kind of bringing up a topic from the dead, but something like this would be very useful. Ideally, you spec out your particular design's constraints in Chisel and Chisel will dump some config file (or something into the Verilog code) that will make sure that everything is interpreted correctly by the desired tool.

I had an issue where the Verilog synthesized properly (passed simulation) only when distributed RAM was inferred, but the timing didn't match what was supported by BRAM (which was inferred by default), so I had to add in the additional synthesis option.