chisel2-deprecated
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ucb-bar
Hi, It would be useful to alow to set custom parameter (verilog backend) to signals and ram. For example with xilinx FPGA : (\* KEEP = "TRUE" *) reg [10:0]...
Attached is [verilator_bug.zip](https://github.com/ucb-bar/chisel/files/798543/verilator_bug.zip), a tiny example that produces the error message below when you run "sbt run". There's not much that can be removed or changed before the problem disappears....
The tester crashed with a segmentation fault Chisel trace is ``` bash [info] Chisel.TestApplicationException: test application exit - exit code 139 [info] at Chisel.Tester.throwExceptionIfDead(Tester.scala:128) [info] at Chisel.Tester.Chisel$Tester$$mwhile(Tester.scala:138) [info] at Chisel.Tester.start(Tester.scala:763)...
Fresh git clone. Running `sbt run` getting this error: ``` drom@drom:~/work/github/usb-bar/chisel> ~/programs/sbt/bin/sbt run [info] Loading project definition from /home/drom/work/github/usb-bar/chisel/project [info] Set current project to chisel (in build file:/home/drom/work/github/usb-bar/chisel/) [info] Running...
Currently, the only way to sanely inject a configuration object into a design is by appending --configInstance [string of config Instance class]. This is passable but the Class.forName(name) call is...
Hi, I am using Synopsys tool to synthesize a verilog netlist generated from Chisel implementation. Tool is not able to map any library cells to reg_files of Queue creating sequential...
With the following verilog, the always @(*) is interpreted as trigger on all input changes. However as there are no inputs, this never triggers. Hence it has the value xxx....
Added arguments to blackbox which are passed through to the module so the clock can be specified in essentially the same way.
These functions are used in the tutorial and manual, but are not explained. A google search has also revealed nothing. Can someone explain what they do, and perhaps add this...
