tree-sitter-verilog
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simple_text_macro_usage
Allow simple_text_macro_usage statements in reasonable places of the grammar:
- [ ] - vector size. a = `WIDTH'b0;
- [ ] - delay value. a <= `DELAY b
I took a look at this for the intergral_number case and ran into a couple of issues.
You cannot put non-terminals inside a token() at present (link). So one cannot reuse simple_text_macro_usage inside binary_number without removing token.
If you remove the token() around one of the integral_number children a large number of seemingly unrelated tests start failing (module - with parameters and ios as an example). I believe this is because of conflicting tokens, but I wasn't able to fix the tests.
You could define a new token inside the token() function of binary_number to represent a simple macro usage, but having simple_text_macro_usage visible in the syntax tree might be useful for highlighting.