verilog-hdl topic

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

dpretet

High throughput JPEG decoder in Verilog for FPGA

ultraembedded

Image Processing Toolbox in Verilog using Basys3 FPGA

Gowtham1729

A complete open-source design-for-testing (DFT) Solution

AUCOHL

System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment

gupta409

5-stage pipelined 32-bit MIPS microprocessor in Verilog

neelkshah

2017级北航计算机学院计算机组成原理课程设计(MIPS CPU)

aptx1231

An efficient implementation of the Viterbi decoding algorithm in Verilog

jfoshea

A simple 8-bit computer build in Verilog.

lightcode

Interface Protocol in Verilog

halftop