asic topic
pygears
HW Design: A Functional Approach
skywater-pdk
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
biriscv
32-bit Superscalar RISC-V CPU
awesome-dv
Awesome ASIC design verification
open-register-design-tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
Embedded-Neural-Network
collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning
systemrdl-compiler
SystemRDL 2.0 language compiler front-end
ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
hiveos-asic
Hive OS client for ASICs