Entity definitions

[tcr]

Borrowing another idea from VHDL (and Rust), it'd be nice to separate the entity definition from its logic/"architecture".

entity SpiMaster {
  in rst: bit,
  in clk: bit,
  in tx_trigger: bit,
  out tx_ready: bit,
  in tx_byte: bit[8],
  out rx_byte: bit[8],
  out spi_clk: bit,
  out spi_tx: bit,
  in spi_rx: bit,
}

impl SpiMaster {
  ...
}

In addition to separating the entity definition, this could go a step further and allow declarations which implicitly generate our wires:

let spi = SpiMaster {
  rst: rst,
  spi_tx: MOSI,
  spi_rx: MISO,
};

let div_idx: uint{..4} = 0;
on clk.negedge {
    reset rst {
        if div_idx == 3 {
            spi.clk <= !spi.clk;
            div_idx <= 0;
        } else {
            div_idx <= div_idx + 1;
        }
    }
}

The question here is whether we should declare all variables, no variables, just in variables, or something else.

[tcr]

Entity definitions and implementations are, for the moment, separated (as above).

Referencing output vars of sub-entities is not yet implemented.