stnolting

There was the idea to implement a new top generic to pass the path to memory init files to the design. Basically, I am ok with this as this could...

@umarcor > Therefore, defining the path through a generic string is the most portable solution. That's not only with regard to multiple simulators but also with regard to different OS,...

I have modified the makefiles and the image generator. A `make hex` will create a plain ASCII hex-char text file `neorv32_exe.hex` that can be used to initialize custom (instruction-)memories. The...

https://github.com/stnolting/neorv32/pull/98#issuecomment-875671484: > > @jeremyherbert > > > Ok, I fetched all of these changes and built it, loaded the newly generated svf and it works great: > > Good to...

> QSPI in the core itself would make a lot of sense, especially if this could eventually be used for execute-in-place. QSPI should be no problem I think. SPI is...

I have implemented a Wishbone-to-SPI bridge supporting XIP: -> #224 It only implements "single-bit" SPI mode so far (no dSPI/qSPI).

That would be pretty cool! I was thinking about some brute force application: Use a soft-core as interface to get a new work package into the SPRAMs, then consecutively load...

> Not for mining, but @tmeissner has this repo of cryptocores: tmeissner/cryptocores. I don't know whether those fit in the UP5K... I cant find any synthesis results there, but that...

> Here you can see it... https://twitter.com/juanmard/status/1405716286601105408 This! Is!! Awesome!!! 🤩:heart: So now we do have a template for dynamic reconfiguration!! :+1: The next cool thing would be to ~~insulate~~...

😄 :+1: The placement might be a problem. But as a workaround we could also use all 4 SPRAMs as simple memory dump module and access them in parallel. So...