stnolting

Hey @ivanholmes. > I am trying to simulate de0-nano-test-setup using Questa Intel FPGA Edition Did you use the [TCL script](https://github.com/stnolting/neorv32-setups/blob/main/quartus/de0-nano-test-setup/create_project.tcl) to setup the project? > [...] it can't find neorv32_application_image.vhd....

> I'll look into it early next week and see how I get on. Great! Keep us updated! This project is intended to work "out-of-the-box" - so we'll make every...

> It turns out that the order of files in the de0-nano-test-setup_run_msim_rtl_vhdl.do file (that Quartus NativeLink generates for Questa) is very important. Some tools can figure out the compile order...

I have never used Quartus NativeLink, so I am not familiar with the simulation flow. I am using AMD ISIM, GHDL and Cadence simulation solutions - all using the file...

It's been a while since we set this up here... As far as I can remember, there are two possible ways to use Yosys with VHDL sources: * Yosys with...

I have never worked with the OSS CAD suite myself - it's still on my to-do list. > I usually load it with the option `-m ghdl' of Yosys. That's...

I still don't understand (again) why the flow still works for me locally. 🤔 > And the README from the osflow directory didn't say it. Do you have any suggestions...

Thanks for adding this! :+1:

Looks good now, thanks again!

This might be the problem: ```tcl set_property enablement_dependency {$XBUS_EN} [ipx::get_bus_interfaces ahb_lite -of_objects [ipx::current_core]] ``` I think Vivado cannot identify your `ahb_*` top ports as AHB-lite interface. You need to stick...