stnolting

> It'll be available in the next release. Is there already a date for it?

Hey @racodond! How can I modify the quality gate requirements? For me, it seems like they're fixed and cannot be altered at all. 🤔 However, I would like to relax...

> So cool! What technology node are you using? It is!! 😅 A 180nm technology and maybe a 130nm technology as well. > So your idea is replacing things like...

FYI Here is a nice pre-defined IP block from Efabless: https://platform.efabless.com/design_catalog/ip_block/40 Actually, this one already has one output register stage.

Hey @mohamedElbouazzati! > Hello world test : This looks good! So the processor seems to operate just fine! :+1: > However, the terminal fails to boot and is stuck at...

That is so cool! Thank you so much! I still want to get into Zephyr too, but I just haven't really gotten around to it yet. Can you recommend a...

@henrikbrixandersen Thanks for the update and all your work! I really appreciate it.

Hey @jeras, sorry for the late repsonse - somehow I completely overlooked this... 🙈 This is a very interesting approach! It really is always a lot of work when the...

> I developed a method for debugging ISA issues by comparing execution logs. We now have a [TRACER](https://stnolting.github.io/neorv32/#_execution_trace_buffer_tracer) that can generate execution logs during simulation. For me, this is very...

> https://github.com/jeras/gdb_server_stub_sv This looks pretty cool! > When I get the C++ version to work again, I will ask you to test it on NEORV32. :+1: > On the CPU...