stnolting

I think this can be closed.

> This is the opposite to how you define AMO instructions as loads (read operations). > To me this seems to indicate, that AMO instructions are seen as writes and...

> Did you consider using the CPU core ALU to implement AMO logic/arithmetic operations? Could you elaborate on your decision process? Yes I did. But the "impact" on the CPU...

Out current bus interface uses a strobe to indidcate valid requests. This signal is high for just one cycle - in contrast to your valid signal which is high until...

> To map this to FPGA/ASIC SRAM, chip enable would be cen = trn. So `trn` is a signal generated by the interconnected andsend to the devices? What if there...

> Write back is a separate stage, so it can align with the 1 clock cycle delay of SRAM. In term of TCB, the system bus is parameterized with DLY=1....

> To me this seems to indicate, that AMO instructions are seen as writes and could trigger a store access-fault exception. Finally, this has been fixed in https://github.com/stnolting/neorv32/pull/1360.

Looks good now! 🚀 Thanks for your help! Now I will take a closer look at the "Quality Profiles".

Hey @racodond. Some questions... I do not understand the configuration of the hierarchy. How to set a specific file as top module to? I have problems understanding the "Only use...

> You do not specify a file name but an entity name. The top module should be set in two locations: Right, my fault. I would like to use the...