srsRAN_Project
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20 hours ago •
srsran
srsran
UE doesn't see the cell with latest SRS RAN and Benetel 550 at 100MHz
Hi Team,
We have recently up RU / split: RAN550-1v1.4.1-NM-25fa970 Split 7.2 Core: Open5GS OS: AzureLinux3 Bandwidth / band: n77, 100 MHz, SCS 30 kHz Antennas: 4x4 & 4x2 Fronthaul: DPDK
We have recently upgraded our Benetel RU to RAN550-1v1.4.1-NM-25fa970 and SRS RAN to 25.4 Release. However, after the upgrade we are having issues with UE attachment. We have tried with Quactel Modems and Iphone15 which used to work earlier but after the upgrade none of them sees the cell.
I have tried multiple configurations but nothing worked. Here is an example config I'm trying:
SRS Config:
cu_cp:
amf:
addr: 192.168.101.11
bind_addr: 0.0.0.0
supported_tracking_areas:
- plmn_list:
- plmn: '99999'
tai_slice_support_list:
- sd: 162
sst: 1
- sd: 163
sst: 1
- sd: 164
sst: 1
- plmn: '00101'
tai_slice_support_list:
- sd: 162
sst: 1
- sd: 163
sst: 1
- sd: 164
sst: 1
tac: 1
security:
nea_pref_list: nea2,nea1,nea3,nea0
cu_up:
ngu:
socket:
- bind_addr: 192.168.110.201
cell_cfg:
dl_arfcn: 676334
band: 77
channel_bandwidth_MHz: 100
common_scs: 30
nof_antennas_dl: 4
nof_antennas_ul: 2
tdd_ul_dl_cfg:
dl_ul_tx_period: 10
nof_dl_slots: 7
nof_dl_symbols: 6
nof_ul_slots: 2
nof_ul_symbols: 4
plmn: "00101" # Replace PLMN and TAC with your core network settings
tac: 1
pci: 1
ssb:
ssb_block_power_dbm: -11
prach:
prach_config_index: 159
prach_root_sequence_index: 1
zero_correlation_zone: 0
pdsch:
mcs_table: qam256
pusch:
mcs_table: qam64
ru_ofh:
t1a_max_cp_dl: 470
t1a_min_cp_dl: 419
t1a_max_cp_ul: 336
t1a_min_cp_ul: 285
t1a_max_up: 345
t1a_min_up: 294
ta4_max: 200
ta4_min: 0
is_prach_cp_enabled: true
compr_method_ul: bfp
compr_bitwidth_ul: 9
compr_method_dl: bfp
compr_bitwidth_dl: 9
compr_method_prach: bfp
compr_bitwidth_prach: 9
enable_ul_static_compr_hdr: false
enable_dl_static_compr_hdr: false
iq_scaling: 20.0
cells:
- network_interface: 0000:86:09.0 # Replace with the DU network interface name (or BDF) for the DU <-> RU connection.
ru_mac_addr: 8c:1f:64:d1:14:bd
du_mac_addr: 00:11:22:33:14:bd # Replace with the MAC address of the DU interface.
enable_promiscuous: false
vlan_tag_up: 9 # Replace with the used CP VLAN.
vlan_tag_cp: 9 # Replace with the used UP VLAN.
prach_port_id: [4,5]
dl_port_id: [0,1,2,3]
ul_port_id: [0,1]
hal:
eal_args: "--lcores (0-8)@(9-23) -a 0000:86:09.0" # Replace the DU network interface name.
expert_phy:
max_request_headroom_slots: 0
max_proc_delay: 4
pusch_dec_max_iterations: 10
expert_execution:
threads:
upper_phy:
pdsch_processor_type: auto
nof_pusch_decoder_threads: 4
nof_ul_threads: 2
nof_dl_threads: 8
metrics:
autostart_stdout_metrics: true
enable_json: true
enable_log: true
periodicity:
du_report_period: 1000
cu_up_report_period: 1000
cu_cp_report_period: 1000
app_usage_report_period: 1000
layers:
enable_ru: true
enable_sched: true
enable_rlc: true
enable_mac: true
enable_pdcp: true
enable_du_low: true
enable_app_usage: true
RU Config:
mimo_mode=1_2_3_4_4x2
downlink_scaling=6
prach_format=short
prach_freq_offset_dynamic=true
prach_freq_offset=1
compression=dynamic_compressed
prach_msg1_freq_start=0
lf_prach_compression_enable=true
cplane_per_symbol_workaround=disabled
cuplane_dl_coupling_sectionID=disabled
flexran_prach_workaround=disabled
dpd_reset_timer=43200
c_plane_du_mac=00:11:22:33:14:bd
u_plane_du_mac=00:11:22:33:14:bd
u_plane_du_vlan_uplink=9
u_plane_du_vlan_downlink=9
c_plane_du_vlan=9
tdd_switching=1500
bandwidth_hz=100000000
centre_frequency_hz=4145000000
tx_power_dbm=24.000000
tdd_pattern_1=DDDDDDDSUU
tdd_pattern_2=
special_slots_symbols=DDDDDDGGGGUUUU
special_slots_symbols1=
special_slots_symbols2=
lf_prach_slot_id=0
dl_tuning_special_slot=0x13b6
cplane_per_symbol_timing=false
non_ideal_c4_timing_enable=false
m_plane_u_plane_config_v16=false
SRS Counters also seem to be lower than the older working release:
root@benetelru:~# kpi.sh
SAMPLE_TIME | RX_TOTAL | RX_ON_TIME | RX_EARLY | RX_LATE | RX_ON_TIME_C | RX_EARLY_C | RX_LATE_C | TX_TOTAL
01:11:55.819828 | 15560 | 14316 | -0 | -0 | 1230 | -0 | -0 | 2400
01:11:56.816314 | 15560 | 14316 | -0 | -0 | 1222 | -0 | -0 | 2400
01:11:57.815704 | 15560 | 14372 | -0 | -0 | 1224 | -0 | -0 | 2400
01:11:58.818620 | 15620 | 14316 | -0 | -0 | 1230 | -0 | -0 | 2400
01:11:59.818093 | 15560 | 14316 | -0 | -0 | 1224 | -0 | -0 | 2400
01:12:00.817580 | 15560 | 14316 | -0 | -0 | 1228 | -0 | -0 | 2400
01:12:01.817832 | 15560 | 14372 | -0 | -0 | 1224 | -0 | -0 | 2400
01:12:02.816585 | 15620 | 14316 | -0 | -0 | 1218 | -0 | -0 | 2400
01:12:03.817653 | 15560 | 14316 | -0 | -0 | 1230 | -0 | -0 | 2400
01:12:04.818360 | 15560 | 14316 | -0 | -0 | 1228 | -0 | -0 | 2400
^C
root@benetelru:~#
TXMeanPower:
root@benetelru:~# TXMeanPower
TX 1 Mean Power: 13.6005 dBm
TX 2 Mean Power: -2.91969 dBm
TX 3 Mean Power: 18.5594 dBm
TX 4 Mean Power: 15.392 dBm
root@benetelru:~#
The error code dpdErrorCode in oru_dpd_stats is also 0.
Can you please guide us to resolve this issue ?
Regards, Ankit
Hello, I have tried this config as well but still the UE doesn't see the cell. These are the same UEs we have tried and tested with Older SRS and Bentel software.
2nd Iteration
RU Config:
cell_cfg:
band: 77
channel_bandwidth_MHz: 100
common_scs: 30
dl_arfcn: 676334
nof_antennas_dl: 4
nof_antennas_ul: 2
pci: 9
plmn: '00101'
prach:
prach_root_sequence_index: 1
prach_config_index: 159
zero_correlation_zone: 0
pusch:
mcs_table: qam256
ssb:
ssb_block_power_dbm: -11
tac: 1
tdd_ul_dl_cfg:
dl_ul_tx_period: 10
nof_dl_slots: 7
nof_dl_symbols: 6
nof_ul_slots: 2
nof_ul_symbols: 4
cells:
- channel_bandwidth_MHz: 100
dl_arfcn: 676334
pci: 9
cu_cp:
amf:
addr: 192.168.101.16
bind_addr: 0.0.0.0
supported_tracking_areas:
- plmn_list:
- plmn: '99999'
tai_slice_support_list:
- sd: 162
sst: 1
- sd: 163
sst: 1
- sd: 164
sst: 1
- plmn: '00101'
tai_slice_support_list:
- sd: 162
sst: 1
- sd: 163
sst: 1
- sd: 164
sst: 1
tac: 1
mobility:
cells:
- nr_cell_id: 6733824
periodic_report_cfg_id: 1
report_configs:
- report_cfg_id: 1
report_interval_ms: 1024
report_type: periodical
security:
nea_pref_list: nea2,nea1,nea3,nea0
cu_up:
ngu:
socket:
- bind_addr: 192.168.110.201
hal:
eal_args: --lcores (0-22)@(9-31) -a 0000:86:11.0
jbpf:
jbpf_agent_cpu: 0
jbpf_agent_policy: 1
jbpf_agent_priority: 30
jbpf_enable_ipc: 0
jbpf_enable_lcm_ipc: 1
jbpf_io_mem_size_mb: 1024
jbpf_ipc_mem_name: jrt_controller
jbpf_lcm_ipc_name: jbpf_lcm_ipc
jbpf_maint_cpu: 0
jbpf_maint_policy: 0
jbpf_maint_priority: 0
jbpf_namespace: jbpf
jbpf_run_path: /tmp
jbpf_standalone_io_in_port: 30400
jbpf_standalone_io_out_ip: 192.168.100.212
jbpf_standalone_io_out_port: 20788
jbpf_standalone_io_policy: 0
jbpf_standalone_io_priority: 0
log:
all_level: warning
filename: ./gnb.log
gtpu_level: warning
mac_level: info
ofh_level: debug
rlc_level: info
rrc_level: info
metrics:
autostart_stdout_metrics: true
ru_ofh:
cells:
- t1a_max_cp_dl: 470
t1a_min_cp_dl: 419
t1a_max_cp_ul: 336
t1a_min_cp_ul: 285
t1a_max_up: 345
t1a_min_up: 294
ta4_max: 200
ta4_min: 0
is_prach_cp_enabled: true # Configures if Control-Plane messages should be used to receive PRACH messages.
compr_method_ul: bfp # Uplink compression method.
compr_bitwidth_ul: 9 # Uplink IQ samples bitwidth after compression.
compr_method_dl: bfp # Downlink compression method.
compr_bitwidth_dl: 9 # Downlink IQ samples bitwidth after compression.
compr_method_prach: bfp # PRACH compression method.
compr_bitwidth_prach: 9 # PRACH IQ samples bitwidth after compression.
enable_ul_static_compr_hdr: false # Configures if the compression header is present for uplink User-Plane messages (false) or not present (true).
enable_dl_static_compr_hdr: false # Configures if the compression header is present for downlink User-Plane messages (false) or not present (true).
iq_scaling: 20 # IQ samples scaling factor applied before compression.
dl_port_id:
- 0
- 1
- 2
- 3
du_mac_addr: 00:11:22:33:14:bd
network_interface: 0000:86:11.0
prach_port_id:
- 4
- 5
ru_bandwidth_MHz: 100
ru_mac_addr: 8c:1f:64:d1:14:bd
ul_port_id:
- 0
- 1
vlan_tag_cp: 9
vlan_tag_up: 9
ru_bandwidth_MHz: 100
RU Config:
# Please place this file in /etc
# Please make sure that parameter values are modified after the = sign without any other format changes
# MIMO mode - the radio can operate in 1_3, 2_4, 1_2_3_4_4x2 or 1_2_3_4_4x4 mode
# For uncompressed mode use only 2x2 configuration (1_2 or 2_4)
# Variable name : mimo_mode
# Valid options : 1_3
# 2_4
# 1_2_3_4_4x2
# 1_2_3_4_4x4
mimo_mode=1_2_3_4_4x2
# FPGA downlink scaling in steps of 6 dB (0, 6, 12 and 18 can be set)
# Variable name : downlink_scaling
# Valid options : 0
# 6
# 12
# 18
downlink_scaling=0
# PRACH format
# Variable name : prach_format
# Valid options : short
# long
prach_format=short
# PRACH frequncy offset dynamic (C-plane Type 3 freqOffset field) / static (using ru_config.cfg file)
# Dynamic LF PRACH is currently not supported
# Static SF PRACH is curently not supported
# Variable name : prach_freq_offset_dynamic
# Valid options : true
# false
prach_freq_offset_dynamic=true
# PRACH frequncy offset (in steps of one half the subcarrier spacings delta_f_Hz) for static configuration
# Currently supported for static LF PRACH configuration only.
# Variable name : prach_freq_offset
# Valid options : +-2*freq_offset_Hz/delta_f_Hz
prach_freq_offset=0
# O-RU Compression settings (note uncompressed mode is not supported when RU is in 4x2 or 4x4 mode)
# Variable name : compression
# Valid options : static_uncompressed
# dynamic_uncompressed
# static_compressed
# dynamic_compressed
compression=dynamic_compressed
# Prach msg1 frequency start. Static (using ru_config.cfg file)
# Currently supported only for LF PRACH static configuration only.
# SF prach msg1FreqStart will read from C-Plane sectionType3 message
# Variable name : prach_msg1_freq_start
# Valid options : 0
# max = 270 (depending on PRACH format and bandwidth)
prach_msg1_freq_start=0
# Long form PRACH compression settings
# Variable name : lf_prach_compression_enable
# Valid options : true
# false
lf_prach_compression_enable=false
# C-Plane per-symbol workaround
# Variable name : cplane_per_symbol_workaround
# Valid options : enabled
# disabled
cplane_per_symbol_workaround=disabled
# CUPLANE dl couplling sectionID
# Variable name : cuplane_dl_coupling_sectionI
# Valid options : enabled
# disabled
cuplane_dl_coupling_sectionID=disabled
# # FlexRAN PRACH workaround (uncompressed PRACH w/ udCompHdr)
# Variable name : flexran_prach_workaround
# Valid options : enabled
# disabled
flexran_prach_workaround=disabled
# DPD reset timer
# Variable name : dpd_reset_timer
# Valid options : Time between DPD resets in seconds, eg. 43200 for 12 hours
dpd_reset_timer=43200
# C-Plane DU MAC address
# Variable name : c_plane_du_mac
# Valid options : A valid MAC address separated by semicolons eg. 00:11:22:33:44:67
c_plane_du_mac=00:11:22:33:14:bd
# U-Plane DU MAC address
# Variable name : u_plane_du_mac
# Valid options : A valid MAC address separated by semicolons eg. 00:11:22:33:44:66
u_plane_du_mac=00:11:22:33:14:bd
# DU VLAN tag control information for uplink U-Plane traffic
# Variable name : u_plane_du_vlan_uplink
# Valid options : Hex number from 1 to fff
u_plane_du_vlan_uplink=9
# DU VLAN tag control information for downlink U-Plane traffic
# Variable name : u_plane_du_vlan_downlink
# Valid options : Hex number from 1 to fff
u_plane_du_vlan_downlink=9
# DU VLAN tag control information for C-Plane traffic
# Variable name : c_plane_du_vlan
# Valid options : Hex number from 1 to fff
c_plane_du_vlan=9
# TDD switching
# Variable name : tdd_switching
# Valid options : Contact Benetel support if changes needed
tdd_switching=1500
# RU bandwidth in Hz
# Variable name : bandwidth_hz
# Valid options : 10000000
# 20000000
# 40000000
# 50000000
# 60000000
# 80000000
# 90000000
# 100000000
bandwidth_hz=100000000
# RU centre frequency in Hz
# Variable name : centre_frequency_hz
# Valid options : check frequency range in /tmp/logs/ru_information
centre_frequency_hz=4145000000
# RU Tx power in dBm
# Variable name : tx_power_dbm
# Valid options : check max output power in /tmp/logs/ru_information or User Guide.
# Range varies between (max output power -20) and max output power
#
tx_power_dbm=24.000000
# Configuration of TDD pattern
# Variable name : tdd_pattern_1
# tdd_pattern_2
# Valid options : Maximum ten slots total, only characters D, S & U, all uppercase, must begin with Downlink slot and contain one or no Special slot.
# Please refer to User Guide for configurations of the required TDD pattern.
tdd_pattern_1=DDDD
tdd_pattern_2=DDDSUU
# Configuration of TDD special slots for TDD patterns (tdd_pattern_1, tdd_pattern_2)
# Variable name : special_slots_symbols
# special_slots_symbols1
# special_slots_symbols2
# Valid options : 14 symbols must be specified, only characters D (Downlink), G (Guard) and
# U (Uplink), all uppercase, must begin with Downlink.
#
# special_slots_symbols is a common configuration for both special slots
# located in tdd_pattern_1 or tdd_pattern_2.
#
# special_slots_symbols_1 corresponds to special slot in tdd_pattern_1.
# special_slots_symbols_2 corresponds to special slot in tdd_pattern_2.
# special_slots_symbols[1/2] parameters overwrite common configuration
# specified by special_slots_symbols.
# Please refer to User Guide for configurations of the required special slot pattern.
special_slots_symbols=DDDDDDGGGGUUUU
# Configure below only when two special slots need to be configured using different symbol patterns
special_slots_symbols1=
special_slots_symbols2=
# LF PRACH SlotID_Flag
# Variable name : lf_prach_slot_id
# Valid options : 0 (LF Prach U-Plane packet Slot Id 0)
# 1 (LF Prach U-Plane packet Slot Id 1)
lf_prach_slot_id=1
# DL_special slot tunning (Internal use)
# Variable name : dl_tuning_special_slot
# Valid range : 0x0:0x13bc
dl_tuning_special_slot=0x13b6
# Configuration of FH C-plane timing reference point defined by ORAN specification
# Variable name : cplane_per_symbol_timing
# Valid options : false - C-plane per slot timing
# (C-plane timing reference point is a slot boundary where corresponding U-plane packets are transmitted)
# true - C-plane per symbol timing
# (C-plane timing reference point is the first corresponding U-plane symbol boundary)
# If not specified, default is false.
cplane_per_symbol_timing=false
# Fix for issues related to non-ideal timing in certain network/synchronization deployment scenarios (eg. C4)
# Variable name : non_ideal_c4_timing_enable
# Valid options : true
# false
non_ideal_c4_timing_enable=false
# Configure M-Plane array carriers activation behavior to align with v16.01 specification
# Variable name : m_plane_u_plane_config_v16
# Valid options : true
# false
m_plane_u_plane_config_v16=false
RU KPI:
root@benetelru:~# kpi.sh
SAMPLE_TIME | RX_TOTAL | RX_ON_TIME | RX_EARLY | RX_LATE | RX_ON_TIME_C | RX_EARLY_C | RX_LATE_C | TX_TOTAL
10:23:38.365305 | 15560 | 14316 | -0 | -0 | 1224 | -0 | -0 | 2400
10:23:39.362421 | 15560 | 14316 | -0 | -0 | 1228 | -0 | -0 | 2400
10:23:40.360562 | 15560 | 14316 | -0 | -0 | 1224 | -0 | -0 | 2376
10:23:41.360273 | 15620 | 14372 | -0 | -0 | 1224 | -0 | -0 | 2400
10:23:42.359925 | 15560 | 14316 | -0 | -0 | 1220 | -0 | -0 | 2400
10:23:43.361215 | 15560 | 14316 | -0 | -0 | 1232 | -0 | -0 | 2408
10:23:44.360877 | 15560 | 14316 | -0 | -0 | 1224 | -0 | -0 | 2392
RU TXMeanPower:
ot@benetelru:~# TXMeanPower
TX 1 Mean Power: 17.9657 dBm
TX 2 Mean Power: -10.5191 dBm
TX 3 Mean Power: 12.3382 dBm
TX 4 Mean Power: 11.1052 dBm
root@benetelru:~#
gnb logs:
2025-10-09T10:24:32.967542 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967545 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '0', symbol_id '0', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967546 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967549 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '0', symbol_id '1', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967550 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967553 [OFH ] [D] Sector#0: packing a downlink type 1 Control-Plane message for slot '745.0' and eAxC '1'
2025-10-09T10:24:32.967553 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '0', symbol_id '2', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967554 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967554 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967556 [OFH ] [D] Quantized IQ samples RMS value of '460.45728'
2025-10-09T10:24:32.967558 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '0', symbol_id '3', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967558 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '1', symbol_id '0', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967559 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967559 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967562 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '0', symbol_id '4', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967563 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967563 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '1', symbol_id '1', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967564 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967565 [OFH ] [D] Quantized IQ samples RMS value of '460.45728'
2025-10-09T10:24:32.967567 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '0', symbol_id '5', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967567 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967568 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '1', symbol_id '2', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967568 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967571 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '0', symbol_id '6', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967572 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '1', symbol_id '3', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967572 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967572 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967576 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '0', symbol_id '7', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967576 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '1', symbol_id '4', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967576 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967577 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967580 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '1', symbol_id '5', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967580 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '0', symbol_id '8', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967581 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967581 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967584 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '0', symbol_id '9', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967584 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '1', symbol_id '6', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967585 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967585 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967588 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '1', symbol_id '7', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967588 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '0', symbol_id '10', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967589 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967589 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967593 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '1', symbol_id '8', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967593 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '0', symbol_id '11', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967594 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967593 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967597 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '1', symbol_id '9', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967597 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '0', symbol_id '12', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967598 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967598 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967601 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '1', symbol_id '10', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967602 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '0', symbol_id '13', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967602 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967602 [OFH ] [D] Sector#0: packing a downlink type 1 Control-Plane message for slot '745.0' and eAxC '2'
2025-10-09T10:24:32.967603 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967606 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '1', symbol_id '11', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967607 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967607 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '2', symbol_id '0', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967608 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967610 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '1', symbol_id '12', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967611 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967611 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '2', symbol_id '1', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967611 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967614 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '1', symbol_id '13', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967614 [OFH ] [D] Sector#0: packing a downlink type 1 Control-Plane message for slot '745.0' and eAxC '3'
2025-10-09T10:24:32.967615 [OFH ] [D] Sector#0: packing a downlink User-Plane message for slot '745.0' and eAxC '2', symbol_id '2', PRB range '0:273', size '7680' bytes
2025-10-09T10:24:32.967615 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
2025-10-09T10:24:32.967616 [OFH ] [D] Packing '273' PRBs inside a User-Plane message using compression type 'BFP' and bitwidth '9'
Can you please help ?
Hey, could you rerun the test with please?
metrics:
enable_log: true
layers:
enable_ru: true
Also please set OFH log to warning, debug is too spammy.
Hi @andrepuschmann , I'm trying with following config now:
I have tested with different values of:
ssb_block_power_dbm ru_reference_level_dBFS subcarrier_rms_backoff_dB p0_nominal_with_grant
cell_cfg:
band: 77
channel_bandwidth_MHz: 100
common_scs: 30
dl_arfcn: 676334
nof_antennas_dl: 4
nof_antennas_ul: 4
pci: 9
plmn: '00101'
prach:
prach_root_sequence_index: 1
prach_config_index: 159
zero_correlation_zone: 0
pdsch:
mcs_table: qam256
olla_target_bler: 0.05
dc_offset: center
pusch:
mcs_table: qam64
olla_target_bler: 0.05
p0_nominal_with_grant: -70 # Needs to be adjusted
min_k2: 2
pucch:
sr_period_ms: 20
min_k1: 2
p0_nominal: -90
csi:
csi_rs_period: 80
ssb:
ssb_block_power_dbm: -11
ssb_period: 20
tac: 1
tdd_ul_dl_cfg:
dl_ul_tx_period: 10
nof_dl_slots: 7
nof_dl_symbols: 6
nof_ul_slots: 2
nof_ul_symbols: 4
cells:
- channel_bandwidth_MHz: 100
dl_arfcn: 676334
pci: 9
cu_cp:
amf:
addr: 192.168.101.11
bind_addr: 0.0.0.0
supported_tracking_areas:
- plmn_list:
- plmn: '99999'
tai_slice_support_list:
- sd: 162
sst: 1
- sd: 163
sst: 1
- sd: 164
sst: 1
- plmn: '00101'
tai_slice_support_list:
- sd: 162
sst: 1
- sd: 163
sst: 1
- sd: 164
sst: 1
tac: 1
mobility:
cells:
- nr_cell_id: 6733824
periodic_report_cfg_id: 1
report_configs:
- report_cfg_id: 1
report_interval_ms: 1024
report_type: periodical
security:
nea_pref_list: nea2,nea1,nea3,nea0
cu_up:
ngu:
socket:
- bind_addr: 192.168.110.201
hal:
eal_args: --lcores (0-22)@(9-31) -a 0000:86:09.0
jbpf:
jbpf_agent_cpu: 0
jbpf_agent_policy: 1
jbpf_agent_priority: 30
jbpf_enable_ipc: 0
jbpf_enable_lcm_ipc: 1
jbpf_io_mem_size_mb: 1024
jbpf_ipc_mem_name: jrt_controller
jbpf_lcm_ipc_name: jbpf_lcm_ipc
jbpf_maint_cpu: 0
jbpf_maint_policy: 0
jbpf_maint_priority: 0
jbpf_namespace: jbpf
jbpf_run_path: /tmp
jbpf_standalone_io_in_port: 30400
jbpf_standalone_io_out_ip: 192.168.100.212
jbpf_standalone_io_out_port: 20788
jbpf_standalone_io_policy: 0
jbpf_standalone_io_priority: 0
log:
all_level: warning
filename: ./gnb.log
gtpu_level: warning
mac_level: info
ofh_level: warning
rlc_level: info
rrc_level: info
metrics:
autostart_stdout_metrics: true
enable_log: true
layers:
enable_ru: true
ru_ofh:
cells:
- t1a_max_cp_dl: 490
t1a_min_cp_dl: 350
t1a_max_cp_ul: 336
t1a_min_cp_ul: 285
t1a_max_up: 280
t1a_min_up: 150
ta4_max: 350
ta4_min: 80
ru_reference_level_dBFS: -6
subcarrier_rms_backoff_dB: 2
is_prach_cp_enabled: true # Configures if Control-Plane messages should be used to receive PRACH messages.
compr_method_ul: bfp # Uplink compression method.
compr_bitwidth_ul: 9 # Uplink IQ samples bitwidth after compression.
compr_method_dl: bfp # Downlink compression method.
compr_bitwidth_dl: 9 # Downlink IQ samples bitwidth after compression.
compr_method_prach: none # PRACH compression method.
compr_bitwidth_prach: 16 # PRACH IQ samples bitwidth after compression.
enable_ul_static_compr_hdr: false # Configures if the compression header is present for uplink User-Plane messages (false) or not present (true).
enable_dl_static_compr_hdr: false # Configures if the compression header is present for downlink User-Plane messages (false) or not present (true).
#iq_scaling: 20.0 # IQ samples scaling factor applied before compression.
dl_port_id:
- 0
- 1
- 2
- 3
du_mac_addr: 00:11:22:33:14:bd
network_interface: 0000:86:09.0
prach_port_id:
- 4
- 5
- 6
- 7
ru_bandwidth_MHz: 100
ru_mac_addr: 8c:1f:64:d1:14:bd
ul_port_id:
- 0
- 1
- 2
- 3
vlan_tag_cp: 9
vlan_tag_up: 9
enable_promiscuous: true
check_link_status: true
ru_bandwidth_MHz: 100
Here are the logs:
2025-10-15T00:48:01.845571 [METRICS ] MAC cell pci=9 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=6usec max=19usec max_slot=635.7] dl_tti_req_latency=[avg=5usec max=18usec max_slot=635.7] tx_data_req_latency=[avg=0usec max=2usec max_slot=608.1] ul_tti_req_latency=[avg=1usec max=15usec max_slot=667.19] slot_ind_latency=[avg=15usec max=49usec max_slot=689.1]
2025-10-15T00:48:01.845597 [METRICS ] Scheduler cell pci=9 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=1600 nof_ul_slots=400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=0 mean_latency=4usec max_latency=14usec max_latency_slot=635.7 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a
2025-10-15T00:48:01.845612 [METRICS ] OFH sector#0 pci=9 received messages stats: rx_total=4800 rx_early=0 rx_on_time=4800 rx_late=0; ether_rx: cpu_usage=0.4% max_latency=0.73us avg_latency=0.91us throughput=23.68Mbps rx_bytes=2959593; ether_tx: cpu_usage=0.5% max_latency=1.39us avg_latency=0.87us throughput=330.70Mbps tx_bytes=41337856; rcv_prach: cpu_usage=0.6% max_latency=20.38us avg_latency=1.32us; rcv_ul: cpu_usage=0.0% max_latency=0.00us avg_latency=0.00us; tx_dl_up: cpu_usage=2.5% dl_up_max_latency=131.45us dl_up_avg_latency=66.17us; tx_dl_cp: cpu_usage=0.0% dl_cp_max_latency=1.92us dl_cp_avg_latency=0.48us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=1.62us ul_cp_avg_latency=0.32us; message_tx: cpu_usage=1.7% max_latency=6.54us avg_latency=0.62us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-10-15T00:48:02.845578 [METRICS ] MAC cell pci=9 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=7usec max=21usec max_slot=736.1] dl_tti_req_latency=[avg=6usec max=19usec max_slot=736.1] tx_data_req_latency=[avg=0usec max=2usec max_slot=736.1] ul_tti_req_latency=[avg=1usec max=16usec max_slot=748.19] slot_ind_latency=[avg=15usec max=46usec max_slot=712.14]
2025-10-15T00:48:02.845601 [METRICS ] Scheduler cell pci=9 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=1600 nof_ul_slots=400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=0 mean_latency=4usec max_latency=15usec max_latency_slot=799.6 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a
2025-10-15T00:48:02.845618 [METRICS ] OFH sector#0 pci=9 received messages stats: rx_total=4800 rx_early=0 rx_on_time=4800 rx_late=0; ether_rx: cpu_usage=0.4% max_latency=0.83us avg_latency=0.92us throughput=23.67Mbps rx_bytes=2959344; ether_tx: cpu_usage=0.5% max_latency=1.38us avg_latency=0.88us throughput=316.93Mbps tx_bytes=39616512; rcv_prach: cpu_usage=0.6% max_latency=16.21us avg_latency=1.31us; rcv_ul: cpu_usage=0.0% max_latency=0.00us avg_latency=0.00us; tx_dl_up: cpu_usage=2.4% dl_up_max_latency=122.74us dl_up_avg_latency=66.38us; tx_dl_cp: cpu_usage=0.0% dl_cp_max_latency=1.84us dl_cp_avg_latency=0.50us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=1.96us ul_cp_avg_latency=0.31us; message_tx: cpu_usage=1.7% max_latency=7.32us avg_latency=0.61us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-10-15T00:48:03.845539 [METRICS ] MAC cell pci=9 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=6usec max=21usec max_slot=896.1] dl_tti_req_latency=[avg=5usec max=19usec max_slot=896.1] tx_data_req_latency=[avg=0usec max=2usec max_slot=848.1] ul_tti_req_latency=[avg=1usec max=16usec max_slot=878.19] slot_ind_latency=[avg=16usec max=47usec max_slot=895.3]
2025-10-15T00:48:03.845563 [METRICS ] Scheduler cell pci=9 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=1600 nof_ul_slots=400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=0 mean_latency=4usec max_latency=14usec max_latency_slot=821.0 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a
2025-10-15T00:48:03.845577 [METRICS ] OFH sector#0 pci=9 received messages stats: rx_total=4800 rx_early=0 rx_on_time=4800 rx_late=0; ether_rx: cpu_usage=0.4% max_latency=0.88us avg_latency=0.91us throughput=23.70Mbps rx_bytes=2959597; ether_tx: cpu_usage=0.5% max_latency=1.37us avg_latency=0.87us throughput=327.59Mbps tx_bytes=40907520; rcv_prach: cpu_usage=0.6% max_latency=9.94us avg_latency=1.30us; rcv_ul: cpu_usage=0.0% max_latency=0.00us avg_latency=0.00us; tx_dl_up: cpu_usage=2.5% dl_up_max_latency=127.95us dl_up_avg_latency=66.13us; tx_dl_cp: cpu_usage=0.0% dl_cp_max_latency=1.69us dl_cp_avg_latency=0.47us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=1.38us ul_cp_avg_latency=0.29us; message_tx: cpu_usage=1.7% max_latency=6.46us avg_latency=0.59us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-10-15T00:48:04.845541 [METRICS ] MAC cell pci=9 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=6usec max=26usec max_slot=928.1] dl_tti_req_latency=[avg=5usec max=24usec max_slot=928.1] tx_data_req_latency=[avg=0usec max=2usec max_slot=928.1] ul_tti_req_latency=[avg=1usec max=15usec max_slot=996.19] slot_ind_latency=[avg=15usec max=46usec max_slot=948.15]
2025-10-15T00:48:04.845565 [METRICS ] Scheduler cell pci=9 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=1600 nof_ul_slots=400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=0 mean_latency=4usec max_latency=19usec max_latency_slot=943.6 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a
2025-10-15T00:48:04.845579 [METRICS ] OFH sector#0 pci=9 received messages stats: rx_total=4800 rx_early=0 rx_on_time=4800 rx_late=0; ether_rx: cpu_usage=0.4% max_latency=0.86us avg_latency=0.92us throughput=23.67Mbps rx_bytes=2959344; ether_tx: cpu_usage=0.5% max_latency=1.79us avg_latency=0.87us throughput=316.93Mbps tx_bytes=39616512; rcv_prach: cpu_usage=0.6% max_latency=13.44us avg_latency=1.31us; rcv_ul: cpu_usage=0.0% max_latency=0.00us avg_latency=0.00us; tx_dl_up: cpu_usage=2.4% dl_up_max_latency=123.23us dl_up_avg_latency=65.29us; tx_dl_cp: cpu_usage=0.0% dl_cp_max_latency=1.58us dl_cp_avg_latency=0.49us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=2.68us ul_cp_avg_latency=0.32us; message_tx: cpu_usage=1.7% max_latency=8.76us avg_latency=0.61us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-10-15T00:48:05.845570 [METRICS ] MAC cell pci=9 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=6usec max=19usec max_slot=40.2] dl_tti_req_latency=[avg=5usec max=18usec max_slot=40.2] tx_data_req_latency=[avg=0usec max=2usec max_slot=1008.1] ul_tti_req_latency=[avg=1usec max=16usec max_slot=62.19] slot_ind_latency=[avg=15usec max=46usec max_slot=14.14]
2025-10-15T00:48:05.845594 [METRICS ] Scheduler cell pci=9 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=1600 nof_ul_slots=400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=0 mean_latency=4usec max_latency=13usec max_latency_slot=1005.17 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a
2025-10-15T00:48:05.845609 [METRICS ] OFH sector#0 pci=9 received messages stats: rx_total=4800 rx_early=0 rx_on_time=4800 rx_late=0; ether_rx: cpu_usage=0.4% max_latency=0.81us avg_latency=0.91us throughput=23.68Mbps rx_bytes=2959527; ether_tx: cpu_usage=0.5% max_latency=1.72us avg_latency=0.87us throughput=330.70Mbps tx_bytes=41337856; rcv_prach: cpu_usage=0.6% max_latency=17.49us avg_latency=1.33us; rcv_ul: cpu_usage=0.0% max_latency=0.00us avg_latency=0.00us; tx_dl_up: cpu_usage=2.5% dl_up_max_latency=125.16us dl_up_avg_latency=64.17us; tx_dl_cp: cpu_usage=0.0% dl_cp_max_latency=2.47us
My UEs are hardly able to see the cell. I moved to different location and its just 5-10% chance that it sees the cell and connect. If I simply switch the config to 40Mhz, its better. The throughput isn't that good but at least there are no issues with Attach.
Hi @ankithmr ,
I noticed the center frequency configured in the RU doesn't match the ARFCN used by the gNB, the frequency should be 4145010000 Hz. Could you give it a try please?
Another thing: please use lf_prach_slot_id=0. It is not important in your tests as you use use short-format PRACH, but in case you try long format in the future - use value 0.
Hi @sauka @andrepuschmann ,
I’ve observed that sometimes the UE is able to detect the cell operating at 100 MHz. In our deployment, the RUs are mounted on the ceiling(multiple floors), and it seems the issue might be related to power configuration parameters. I’ve noticed that UEs located on the same floor—just a few meters away from the RU—are often unable to detect the cell at all. However, there are instances when UEs on the floor above can detect the cell and even attach successfully. This doesn’t happen consistently, but roughly 30-40% of the time these UEs just above on the other floor are able to see the cell.
I also had a discussion with Benetel Team and they mentioned that SRS validated ceiling mounted RU units. Could you please advise if there are any parameter tuning recommendations to improve this behaviour?
Can you please suggest a way forward ?
Hi @ankithmr,
Your observations indicate that the RU transmits too much power. We have recently tested srsRAN with Benetel R550 and a COTS UE located close to the RU - here are the settings that worked very well in those tests:
ru_reference_level_dBFS: -12 # 4T4R; -9 for 4T2R, -12 for 2T2R
subcarrier_rms_backoff_dB: 0
Hi @sauka , Thanks for your response. I have tried it but still the same issue. I'm trying with a n77 Supported COTS UE and a Quactel modem. Can you check if there are any other parameters which are problematic ? Would you mind sharing the working config for your lab RU and SRS ?
Hi @ismagom , Its definitely radiating. Now somehow the UE can sometimes (10 to 15% of the time)see the cell. I tried with multiple values and that's why I would like to see if there are any parameters causing the issue. It seems related to the power but not sure how to tune it.
Here are the logs of some of the attempts:
Attempt 1:
|--------------------DL---------------------|-------------------------UL----------------------------------
pci rnti | cqi ri mcs brate ok nok (%) dl_bs | pusch rsrp ri mcs brate ok nok (%) bsr ta phr
9 4601 | 11 3.0 13 7.3k 4 4 50% 0 | 30.6 -0.3 1 26 4.22k 1 7 87% 0 178n -32
9 4601 | 11 3.0 17 154k 122 275 69% 53 | 30.9 ovl 1 28 0 0 73 100% 0 214n -32
Attempt 2:
|--------------------DL---------------------|-------------------------UL----------------------------------
pci rnti | cqi ri mcs brate ok nok (%) dl_bs | pusch rsrp ri mcs brate ok nok (%) bsr ta phr
9 4601 | 10 3.0 15 15k 9 8 47% 0 | 25.1 -0.2 1 27 4.22k 1 20 95% 0 448n -32
9 4601 | 10 3.0 13 155k 134 334 71% 53 | 21.2 ovl 1 27 0 0 55 100% 0 577n -32
GNB logs:
x_latency=3.58us ul_cp_avg_latency=0.33us; message_tx: cpu_usage=2.7% max_latency=9.00us avg_latency=0.95us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-11T15:34:26.525544 [METRICS ] MAC cell pci=9 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=10usec max=30usec max_slot=944.1] dl_tti_req_latency=[avg=5usec max=28usec max_slot=944.1] tx_data_req_latency=[avg=0usec max=1usec max_slot=0.1] ul_tti_req_latency=[avg=5usec max=16usec max_slot=1021.16] slot_ind_latency=[avg=14usec max=47usec max_slot=938.15]
2025-11-11T15:34:26.525567 [METRICS ] Scheduler cell pci=9 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=600 nof_ul_slots=1400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=0 mean_latency=7usec max_latency=22usec max_latency_slot=987.12 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a
2025-11-11T15:34:26.525585 [METRICS ] OFH sector#0 pci=9 received messages stats: rx_total=4800 rx_early=0 rx_on_time=4800 rx_late=0; ether_rx: cpu_usage=0.5% max_latency=0.48us avg_latency=1.00us throughput=23.68Mbps rx_bytes=2956860; ether_tx: cpu_usage=1.2% max_latency=1.44us avg_latency=0.93us throughput=709.86Mbps tx_bytes=88644096; rcv_prach: cpu_usage=0.6% max_latency=16.40us avg_latency=1.19us; rcv_ul: cpu_usage=0.0% max_latency=0.00us avg_latency=0.00us; tx_dl_up: cpu_usage=5.4% dl_up_max_latency=135.07us dl_up_avg_latency=65.04us; tx_dl_cp: cpu_usage=0.0% dl_cp_max_latency=8.36us dl_cp_avg_latency=0.45us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=1.11us ul_cp_avg_latency=0.29us; message_tx: cpu_usage=2.6% max_latency=6.69us avg_latency=0.94us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-11T15:34:27.525544 [METRICS ] MAC cell pci=9 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=10usec max=31usec max_slot=48.1] dl_tti_req_latency=[avg=5usec max=29usec max_slot=48.1] tx_data_req_latency=[avg=0usec max=3usec max_slot=16.1] ul_tti_req_latency=[avg=5usec max=16usec max_slot=95.6] slot_ind_latency=[avg=14usec max=46usec max_slot=58.12]
2025-11-11T15:34:27.525588 [METRICS ] Scheduler cell pci=9 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=600 nof_ul_slots=1400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=0 mean_latency=7usec max_latency=24usec max_latency_slot=55.12 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a
2025-11-11T15:34:27.525604 [METRICS ] OFH sector#0 pci=9 received messages stats: rx_total=4800 rx_early=0 rx_on_time=4800 rx_late=0; ether_rx: cpu_usage=0.5% max_latency=0.62us avg_latency=1.02us throughput=23.68Mbps rx_bytes=2956860; ether_tx: cpu_usage=1.2% max_latency=1.90us avg_latency=0.93us throughput=710.11Mbps tx_bytes=88674816; rcv_prach: cpu_usage=0.6% max_latency=13.89us avg_latency=1.22us; rcv_ul: cpu_usage=0.0% max_latency=0.00us avg_latency=0.00us; tx_dl_up: cpu_usage=5.5% dl_up_max_latency=149.78us dl_up_avg_latency=66.54us; tx_dl_cp: cpu_usage=0.0% dl_cp_max_latency=3.16us dl_cp_avg_latency=0.47us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=1.87us ul_cp_avg_latency=0.32us; message_tx: cpu_usage=2.7% max_latency=8.52us avg_latency=0.95us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-11T15:34:28.525548 [METRICS ] MAC cell pci=9 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=10usec max=32usec max_slot=128.1] dl_tti_req_latency=[avg=5usec max=30usec max_slot=128.1] tx_data_req_latency=[avg=0usec max=2usec max_slot=128.1] ul_tti_req_latency=[avg=5usec max=15usec max_slot=105.15] slot_ind_latenc
y=[avg=14usec max=45usec max_slot=126.18]
2025-11-11T15:34:28.525572 [METRICS ] Scheduler cell pci=9 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=600 nof_ul_slots=1400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=0 mean_latency=7usec max_latency=22usec max_latency_slot=114.12 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a
2025-11-11T15:34:28.525586 [METRICS ] OFH sector#0 pci=9 received messages stats: rx_total=4800 rx_early=0 rx_on_time=4800 rx_late=0; ether_rx: cpu_usage=0.5% max_latency=0.60us avg_latency=1.02us throughput=23.65Mbps rx_bytes=2956800; ether_tx: cpu_usage=1.2% max_latency=1.82us avg_latency=0.93us throughput=709.40Mbps tx_bytes=88674816; rcv_prach: cpu_usage=0.6% max_latency=15.56us avg_latency=1.22us; rcv_ul: cpu_usage=0.0% max_latency=0.00us avg_latency=0.00us; tx_dl_up: cpu_usage=5.4% dl_up_max_latency=154.86us dl_up_avg_latency=65.40us; tx_dl_cp: cpu_usage=0.0% dl_cp_max_latency=3.11us dl_cp_avg_latency=0.44us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=2.64us ul_cp_avg_latency=0.30us; message_tx: cpu_usage=2.6% max_latency=8.82us avg_latency=0.94us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-11T15:34:29.525556 [METRICS ] MAC cell pci=9 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=10usec max=31usec max_slot=288.1] dl_tti_req_latency=[avg=5usec max=29usec max_slot=253.12] tx_data_req_latency=[avg=0usec max=2usec max_slot=256.1] ul_tti_req_latency=[avg=5usec max=15usec max_slot=303.6] slot_ind_latency=[avg=14usec max=47usec max_slot=293.6]
2025-11-11T15:34:29.525579 [METRICS ] Scheduler cell pci=9 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=600 nof_ul_slots=1400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=0 mean_latency=7usec max_latency=27usec max_latency_slot=253.12 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a
2025-11-11T15:34:29.525593 [METRICS ] OFH sector#0 pci=9 received messages stats: rx_total=4800 rx_early=0 rx_on_time=4800 rx_late=0; ether_rx: cpu_usage=0.5% max_latency=0.43us avg_latency=1.02us throughput=23.66Mbps rx_bytes=2957060; ether_tx: cpu_usage=1.2% max_latency=1.86us avg_latency=0.93us throughput=712.84Mbps tx_bytes=89105152; rcv_prach: cpu_usage=0.6% max_latency=13.04us avg_latency=1.24us; rcv_ul: cpu_usage=0.0% max_latency=0.00us avg_latency=0.00us; tx_dl_up: cpu_usage=5.4% dl_up_max_latency=133.05us dl_up_avg_latency=65.36us; tx_dl_cp: cpu_usage=0.0% dl_cp_max_latency=1.21us dl_cp_avg_latency=0.45us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=2.35us ul_cp_avg_latency=0.31us; message_tx: cpu_usage=2.6% max_latency=8.80us avg_latency=0.94us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-11T15:34:30.525550 [METRICS ] MAC cell pci=9 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=10usec max=38usec max_slot=384.1] dl_tti_req_latency=[avg=5usec max=35usec max_slot=384.1] tx_data_req_latency=[avg=0usec max=3usec max_slot=384.1] ul_tti_req_latency=[avg=5usec max=16usec max_slot=324.5] slot_ind_latency=[avg=13usec max=47usec max_slot=341.0]
2025-11-11T15:34:30.525577 [METRICS ] Scheduler cell pci=9 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=600 nof_ul_slots=1400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=0 mean_latency=7usec max_latency=25usec max_latency_slot=335.12 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a
2025-11-11T15:34:30.525616 [METRICS ] OFH sector#0 pci=9 received messages stats: rx_total=4800 rx_early=0 rx_on_time=4800 rx_late=0; ether_rx: cpu_usage=0.5% max_latency=0.64us avg_latency=1.01us throughput=23.68Mbps rx_bytes=2956800; ether_tx: cpu_usage=1.2% max_latency=1.95us avg_latency=0.93us throughput=710.11Mbps tx_bytes=88674816; rcv_prach: cpu_usage=0.6% max_latency=13.91us avg_latency=1.24us; rcv_ul: cpu_usage=0.0% max_latency=0.00us avg_latency=0.00us; tx_dl_up: cpu_usage=5.4% dl_up_max_latency=148.01us dl_up_avg_latency=66.00us; tx_dl_cp: cpu_usage=0.0% dl_cp_max_latency=1.38us dl_cp_avg_latency=0.50us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=14.29us ul_cp_avg_latency=0.38us; message_tx: cpu_usage=2.8% max_latency=8.76us avg_latency=1.00us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-11T15:34:31.525546 [METRICS ] MAC cell pci=9 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=10usec max=34usec max_slot=416.1] dl_tti_req_latency=[avg=5usec max=32usec max_slot=416.1] tx_data_req_latency=[avg=0usec max=3usec max_slot=432.1] ul_tti_req_latency=[avg=5usec max=15usec max_slot=412.13] slot_ind_latency=[avg=13usec max=47usec max_slot=475.10]
2025-11-11T15:34:31.525569 [METRICS ] Scheduler cell pci=9 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=600 nof_ul_slots=1400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=0 mean_latency=7usec max_latency=25usec max_latency_slot=455.12 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a
2025-11-11T15:34:31.525587 [METRICS ] OFH sector#0 pci=9 received messages stats: rx_total=4800 rx_early=0 rx_on_time=4800 rx_late=0; ether_rx: cpu_usage=0.5% max_latency=0.67us avg_latency=1.01us throughput=23.68Mbps rx_bytes=2956800; ether_tx: cpu_usage=1.2% max_latency=1.79us avg_latency=0.92us throughput=710.11Mbps tx_bytes=88674816; rcv_prach: cpu_usage=0.6% max_latency=13.61us avg_latency=1.24us; rcv_ul: cpu_usage=0.0% max_latency=0.00us avg_latency=0.00us; tx_dl_up: cpu_usage=5.5% dl_up_max_latency=144.97us dl_up_avg_latency=66.13us; tx_dl_cp: cpu_usage=0.0% dl_cp_max_latency=1.70us dl_cp_avg_latency=0.47us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=1.24us ul_cp_avg_latency=0.32us; message_tx: cpu_usage=2.7% max_latency=8.25us avg_latency=0.96us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-11T15:34:32.525565 [METRICS ] MAC cell pci=9 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=10usec max=32usec max_slot=512.12] dl_tti_req_latency=[avg=5usec max=31usec max_slot=512.12] tx_data_req_latency=[avg=0usec max=2usec max_slot=576.1] ul_tti_req_latency=[avg=5usec max=16usec max_slot=527.6] slot_ind_latency=[avg=13usec max=44usec max_slot=592.16]
2025-11-11T15:34:32.525614 [METRICS ] Scheduler cell pci=9 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=600 nof_ul_slots=1400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=0 mean_latency=7usec max_latency=27usec max_latency_slot=531.12 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a
2025-11-11T15:34:32.525630 [METRICS ] OFH sector#0 pci=9 received messages stats: rx_total=4800 rx_early=0 rx_on_time=4800 rx_late=0; ether_rx: cpu_usage=0.5% max_latency=0.52us avg_latency=1.01us throughput=23.65Mbps rx_bytes=2956800; ether_tx: cpu_usage=1.2% max_latency=1.74us avg_latency=0.92us throughput=709.64Mbps tx_bytes=88705536; rcv_prach: cpu_usage=0.6% max_latency=17.57us avg_latency=1.22us; rcv_ul: cpu_usage=0.0% max_latency=0.00us avg_latency=0.00us; tx_dl_up: cpu_usage=5.4% dl_up_max_latency=143.04us dl_up_avg_latency=65.92us; tx_dl_cp: cpu_usage=0.0% dl_cp_max_latency=1.19us dl_cp_avg_latency=0.45us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=2.88us ul_cp_avg_latency=0.31us; message_tx: cpu_usage=2.6% max_latency=8.04us avg_latency=0.94us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-11T15:34:33.524562 [METRICS ] MAC cell pci=9 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=10usec max=32usec max_slot=608.1] dl_tti_req_latency=[avg=5usec max=29usec max_slot=632.2] tx_data_req_latency=[avg=0usec max=2usec max_slot=608.1] ul_tti_req_latency=[avg=5usec max=15usec max_slot=655.6] slot_ind_latency=[avg=14usec max=46usec max_slot=680.8]
2025-11-11T15:34:33.524584 [METRICS ] Scheduler cell pci=9 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=600 nof_ul_slots=1400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=0 mean_latency=7usec max_latency=26usec max_latency_slot=632.2 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a
2025-11-11T15:34:33.524615 [METRICS ] OFH sector#0 pci=9 received messages stats: rx_total=4800 rx_early=0 rx_on_time=4800 rx_late=0; ether_rx: cpu_usage=0.5% max_latency=0.89us avg_latency=1.02us throughput=23.70Mbps rx_bytes=2956860; ether_tx: cpu_usage=1.2% max_latency=1.72us avg_latency=0.93us throughput=708.60Mbps tx_bytes=88398336; rcv_prach: cpu_usage=0.6% max_latency=14.93us avg_latency=1.19us; rcv_ul: cpu_usage=0.0% max_latency=0.00us avg_latency=0.00us; tx_dl_up: cpu_usage=5.4% dl_up_max_latency=131.73us dl_up_avg_latency=64.69us; tx_dl_cp: cpu_usage=0.0% dl_cp_max_latency=1.12us dl_cp_avg_latency=0.43us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=3.09us ul_cp_avg_latency=0.30us; message_tx: cpu_usage=2.6% max_latency=7.88us avg_latency=0.94us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-11T15:34:34.525544 [METRICS ] MAC cell pci=9 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=10usec max=31usec max_slot=736.1] dl_tti_req_latency=[avg=5usec max=29usec max_slot=736.1] tx_data_req_latency=[avg=0usec max=2usec max_slot=800.1] ul_tti_req_latency=[avg=5usec max=16usec max_slot=780.15] slot_ind_latency=[avg=13usec max=45usec max_slot=728.15]
2025-11-11T15:34:34.525569 [METRICS ] Scheduler cell pci=9 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=600 nof_ul_slots=1400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=0 mean_latency=7usec max_latency=23usec max_latency_slot=706.12 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a
2025-11-11T15:34:34.525583 [METRICS ] OFH sector#0 pci=9 received messages stats: rx_total=4800 rx_early=0 rx_on_time=4800 rx_late=0; ether_rx: cpu_usage=0.5% max_latency=0.85us avg_latency=1.02us throughput=23.65Mbps rx_bytes=2956860; ether_tx: cpu_usage=1.2% max_latency=1.99us avg_latency=0.93us throughput=714.81Mbps tx_bytes=89350912; rcv_prach: cpu_usage=0.6% max_latency=17.18us avg_latency=1.21us; rcv_ul: cpu_usage=0.0% max_latency=0.00us avg_latency=0.00us; tx_dl_up: cpu_usage=5.4% dl_up_max_latency=140.88us dl_up_avg_latency=65.53us; tx_dl_cp: cpu_usage=0.0% dl_cp_max_latency=2.64us dl_cp_avg_latency=0.44us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=1.17us ul_cp_avg_latency=0.28us; message_tx: cpu_usage=2.6% max_latency=9.08us avg_latency=0.94us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-11T15:34:35.525548 [METRICS ] MAC cell pci=9 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=10usec max=34usec max_slot=848.1] dl_tti_req_latency=[avg=5usec max=32usec max_slot=848.1] tx_data_req_latency=[avg=0usec max=2usec max_slot=816.1] ul_tti_req_latency=[avg=5usec max=17usec max_slot=848.4] slot_ind_latency=[avg=14usec max=49usec max_slot=841.10]
2025-11-11T15:34:35.525574 [METRICS ] Scheduler cell pci=9 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=600 nof_ul_slots=1400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=0 mean_latency=7usec max_latency=23usec max_latency_slot=898.12 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a
2025-11-11T15:34:35.525587 [METRICS ] OFH sector#0 pci=9 received messages stats: rx_total=4800 rx_early=0 rx_on_time=4800 rx_late=0; ether_rx: cpu_usage=0.5% max_latency=0.36us avg_latency=1.01us throughput=23.65Mbps rx_bytes=2956860; ether_tx: cpu_usage=1.2% max_latency=1.79us avg_latency=0.93us throughput=709.40Mbps tx_bytes=88674816; rcv_prach: cpu_usage=0.6% max_latency=13.06us avg_latency=1.23us; rcv_ul: cpu_usage=0.0% max_latency=0.00us avg_latency=0.00us; tx_dl_up: cpu_usage=5.3% dl_up_max_latency=129.29us dl_up_avg_latency=64.80us; tx_dl_cp: cpu_usage=0.0% dl_cp_max_latency=1.00us dl_cp_avg_latency=0.44us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=2.82us ul_cp_avg_latency=0.31us; message_tx: cpu_usage=2.6% max_latency=8.62us avg_latency=0.94us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-11T15:34:36.525548 [METRICS ] MAC cell pci=9 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=10usec max=28usec max_slot=976.1] dl_tti_req_latency=[avg=5usec max=26usec max_slot=976.1] tx_data_req_latency=[avg=0usec max=2usec max_slot=912.1] ul_tti_req_latency=[avg=5usec max=14usec max_slot=918.4] slot_ind_latency=[avg=14usec max=46usec max_slot=1002.8]
2025-11-11T15:34:36.525587 [METRICS ] Scheduler cell pci=9 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=600 nof_ul_slots=1400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=0 mean_latency=7usec max_latency=21usec max_latency_slot=913.2 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a
2025-11-11T15:34:36.525603 [METRICS ] OFH sector#0 pci=9 received messages stats: rx_total=4800 rx_early=0 rx_on_time=4800 rx_late=0; ether_rx: cpu_usage=0.5% max_latency=0.52us avg_latency=1.02us throughput=23.65Mbps rx_bytes=2956860; ether_tx: cpu_usage=1.2% max_latency=2.99us avg_latency=0.94us throughput=709.40Mbps tx_bytes=88674816; rcv_prach: cpu_usage=0.6% max_latency=11.69us avg_latency=1.19us; rcv_ul: cpu_usage=0.0% max_latency=0.00us avg_latency=0.00us; tx_dl_up: cpu_usage=5.3% dl_up_max_latency=165.30us dl_up_avg_latency=64.18us; tx_dl_cp: cpu_usage=0.0% dl_cp_max_latency=1.02us dl_cp_avg_latency=0.44us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=0.99us ul_cp_avg_latency=0.29us; message_tx: cpu_usage=2.6% max_latency=12.88us avg_latency=0.94us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-11T15:34:37.525559 [METRICS ] MAC cell pci=9 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=10usec max=32usec max_slot=64.1] dl_tti_req_latency=[avg=5usec max=29usec max_slot=64.1] tx_data_req_latency=[avg=0usec max=2usec max_slot=16.1] ul_tti_req_latency=[avg=5usec max=18usec max_slot=31.6] slot_ind_latency=[avg=13usec max=48usec max_slot=53.2]
2025-11-11T15:34:37.525593 [METRICS ] Scheduler cell pci=9 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=600 nof_ul_slots=1400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=0 mean_latency=7usec max_latency=23usec max_latency_slot=1004.2 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a
2025-11-11T15:34:37.525620 [METRICS ] OFH sector#0 pci=9 received messages stats: rx_total=4800 rx_early=0 rx_on_time=4800 rx_late=0; ether_rx: cpu_usage=0.5% max_latency=0.53us avg_latency=1.01us throughput=23.65Mbps rx_bytes=2956800; ether_tx: cpu_usage=1.2% max_latency=2.00us avg_latency=0.93us throughput=712.84Mbps tx_bytes=89105152; rcv_prach: cpu_usage=0.6% max_latency=15.70us avg_latency=1.24us; rcv_ul: cpu_usage=0.0% max_latency=0.00us avg_latency=0.00us; tx_dl_up: cpu_usage=5.4% dl_up_max_latency=121.89us dl_up_avg_latency=65.29us; tx_dl_cp: cpu_usage=0.0% dl_cp_max_latency=1.08us dl_cp_avg_latency=0.45us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=2.90us ul_cp_avg_latency=0.30us; message_tx: cpu_usage=2.6% max_latency=9.02us avg_latency=0.95us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-11T15:34:38.525549 [METRICS ] MAC cell pci=9 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=10usec max=28usec max_slot=125.0] dl_tti_req_latency=[avg=5usec max=28usec max_slot=125.0] tx_data_req_latency=[avg=0usec max=2usec max_slot=80.1] ul_tti_req_latency=[avg=5usec max=14usec max_slot=94.4] slot_ind_latency=[avg=13usec max=45usec max_slot=118.0]
2025-11-11T15:34:38.525586 [METRICS ] Scheduler cell pci=9 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=600 nof_ul_slots=1400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=0 mean_latency=7usec max_latency=23usec max_latency_slot=98.12 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a
2025-11-11T15:34:38.525601 [METRICS ] OFH sector#0 pci=9 received messages stats: rx_total=4800 rx_early=0 rx_on_time=4800 rx_late=0; ether_rx: cpu_usage=0.5% max_latency=0.42us avg_latency=1.01us throughput=23.68Mbps rx_bytes=2956800; ether_tx: cpu_usage=1.2% max_latency=3.04us avg_latency=0.93us throughput=710.11Mbps tx_bytes=88674816; rcv_prach: cpu_usage=0.6% max_latency=13.61us avg_latency=1.20us; rcv_ul: cpu_usage=0.0% max_latency=0.00us avg_latency=0.00us; tx_dl_up: cpu_usage=5.3% dl_up_max_latency=142.33us dl_up_avg_latency=64.79us; tx_dl_cp: cpu_usage=0.0% dl_cp_max_latency=1.07us dl_cp_avg_latency=0.44us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=2.81us ul_cp_avg_latency=0.31us; message_tx: cpu_usage=2.7% max_latency=13.18us avg_latency=0.95us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-11T15:34:39.525537 [METRICS ] MAC cell pci=9 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=10usec max=30usec max_slot=224.1] dl_tti_req_latency=[avg=5usec max=28usec max_slot=224.1] tx_data_req_latency=[avg=0usec max=2usec max_slot=256.1] ul_tti_req_latency=[avg=5usec max=16usec max_slot=239.6] slot_ind_latency=[avg=14usec max=45usec max_slot=255.4]
2025-11-11T15:34:39.525562 [METRICS ] Scheduler cell pci=9 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=600 nof_ul_slots=1400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=0 mean_latency=7usec max_latency=23usec max_latency_slot=210.2 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a
2025-11-11T15:34:39.525578 [METRICS ] OFH sector#0 pci=9 received messages stats: rx_total=4800 rx_early=0 rx_on_time=4800 rx_late=0; ether_rx: cpu_usage=0.5% max_latency=0.38us avg_latency=1.01us throughput=23.68Mbps rx_bytes=2956800; ether_tx: cpu_usage=1.2% max_latency=1.82us avg_latency=0.93us throughput=710.11Mbps tx_bytes=88674816; rcv_prach: cpu_usage=0.6% max_latency=13.99us avg_latency=1.21us; rcv_ul: cpu_usage=0.0% max_latency=0.00us avg_latency=0.00us; tx_dl_up: cpu_usage=5.4% dl_up_max_laten
cy=144.66us dl_up_avg_latency=65.13us; tx_dl_cp: cpu_usage=0.0% dl_cp_max_latency=3.02us dl_cp_avg_latency=0.45us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=1.26us ul_cp_avg_latency=0.31us; message_tx: cpu_usage=2.6% max_latency=8.37us avg_latency=0.94us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-11T15:34:40.525544 [METRICS ] MAC cell pci=9 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=10usec max=35usec max_slot=288.1] dl_tti_req_latency=[avg=5usec max=33usec max_slot=288.1] tx_data_req_latency=[avg=0usec max=3usec max_slot=304.1] ul_tti_req_latency=[avg=5usec max=15usec max_slot=317.3] slot_ind_latency=[avg=14usec max=47usec max_slot=336.2]
2025-11-11T15:34:40.525593 [METRICS ] Scheduler cell pci=9 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=600 nof_ul_slots=1400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=0 mean_latency=7usec max_latency=25usec max_latency_slot=293.2 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a
2025-11-11T15:34:40.525606 [METRICS ] OFH sector#0 pci=9 received messages stats: rx_total=4800 rx_early=0 rx_on_time=4800 rx_late=0; ether_rx: cpu_usage=0.5% max_latency=0.44us avg_latency=1.01us throughput=23.65Mbps rx_bytes=2956800; ether_tx: cpu_usage=1.2% max_latency=1.74us avg_latency=0.94us throughput=709.40Mbps tx_bytes=88674816; rcv_prach: cpu_usage=0.6% max_latency=15.94us avg_latency=1.20us; rcv_ul: cpu_usage=0.0% max_latency=0.00us avg_latency=0.00us; tx_dl_up: cpu_usage=5.4% dl_up_max_latency=128.66us dl_up_avg_latency=65.37us; tx_dl_cp: cpu_usage=0.0% dl_cp_max_latency=1.23us dl_cp_avg_latency=0.44us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=1.00us ul_cp_avg_latency=0.31us; message_tx: cpu_usage=2.6% max_latency=8.22us avg_latency=0.94us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-11T15:34:41.477531 [RLC ] [W] du=0 ue=0 SRB1 DL: Reached maximum number of RETX. sn=0 retx_count=8
2025-11-11T15:34:41.477540 [DU-MNG ] [W] ue=0: RLF detected with cause="RLC max ReTxs reached". Timer of 1000 msec to release UE started...
2025-11-11T15:34:41.525615 [METRICS ] MAC cell pci=9 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=12usec max=56usec max_slot=435.1] dl_tti_req_latency=[avg=6usec max=52usec max_slot=435.1] tx_data_req_latency=[avg=0usec max=8usec max_slot=435.10] ul_tti_req_latency=[avg=5usec max=26usec max_slot=430.6] slot_ind_latency=[avg=13usec max=46usec max_slot=426.10]
2025-11-11T15:34:41.525627 [METRICS ] Scheduler cell pci=9 metrics: total_dl_brate=17.0kbps total_ul_brate=4.00kbps nof_prbs=273 nof_dl_slots=600 nof_ul_slots=1400 nof_prach_preambles=1 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0.0367 puschs_per_slot=0.0386 failed_pdcch=0 failed_uci=0 nof_ues=1 mean_latency=8usec max_latency=40usec max_latency_slot=435.1 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=1 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 max_crc_delay=3.5ms max_ce_delay=3.5ms max_pucch_harq_delay=3ms avg_prach_delay=7ms events=[{rnti=0x4602 slot=431.5 type=ue_create}]
2025-11-11T15:34:41.525638 [METRICS ] Scheduler UE pci=9 rnti=0x4602 metrics: cqi=10 dl_ri=2.4 dl_mcs=15 dl_brate=17.7kbps dl_nof_ok=12 dl_nof_nok=10 dl_error_rate=45% dl_bs=0 dl_nof_prbs=92 pusch_snr_db=30.3 pusch_rsrp_db=-0.3 ul_ri=1 ul_mcs=28 ul_brate=4.22kbps ul_nof_ok=1 ul_nof_nok=51 ul_error_rate=98% ul_nof_prbs=336 bsr=0 sr_count=12 f0f1_invalid_harqs=0 f2f3f4_invalid_harqs=0 f2f3f4_invalid_csis=1 pusch_invalid_harqs=0 pusch_invalid_csis=0 ta=319ns srs_ta=n/a last_phr=-32 avg_ul_ce_delay=3.5ms max_ul_ce_delay=3.5ms avg_crc_delay=3.04ms max_crc_delay=3.5ms avg_pusch_harq_delay=n/a max_pusch_harq_delay=n/a avg_pucch_harq_delay=3ms max_pucch_harq_delay=3ms
2025-11-11T15:34:41.525653
[METRICS ] OFH sector#0 pci=9 received messages stats: rx_total=11856 rx_early=0 rx_on_time=11856 rx_late=0; ether_rx: cpu_usage=0.6% max_latency=0.84us avg_latency=0.47us throughput=457.18Mbps rx_bytes=57146880; ether_tx: cpu_usage=1.4% max_latency=1.66us avg_latency=0.91us throughput=834.84Mbps tx_bytes=104355072; rcv_prach: cpu_usage=0.6% max_latency=13.77us avg_latency=1.18us; rcv_ul: cpu_usage=5.0% max_latency=27.98us avg_latency=7.03us; tx_dl_up: cpu_usage=6.4% dl_up_max_latency=145.72us dl_up_avg_latency=63.74us; tx_dl_cp: cpu_usage=0.0% dl_cp_max_latency=1.45us dl_cp_avg_latency=0.46us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=2.47us ul_cp_avg_latency=0.32us; message_tx: cpu_usage=2.9% max_latency=7.59us avg_latency=1.04us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-11T15:34:42.525596 [METRICS ] MAC cell pci=9 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=1 wall_clock_latency=[avg=17usec max=67usec max_slot=487.12] dl_tti_req_latency=[avg=10usec max=64usec max_slot=487.12] tx_data_req_latency=[avg=0usec max=4usec max_slot=558.11] ul_tti_req_latency=[avg=6usec max=22usec max_slot=492.13] slot_ind_latency=[avg=13usec max=46usec max_slot=485.14]
2025-11-11T15:34:42.525606 [METRICS ] Scheduler cell pci=9 metrics: total_dl_brate=143kbps total_ul_brate=4.00kbps nof_prbs=273 nof_dl_slots=600 nof_ul_slots=1400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=3 pusch_rbs_per_slot=0 pdschs_per_slot=0.995 puschs_per_slot=0.0186 failed_pdcch=0 failed_uci=0 nof_ues=1 mean_latency=11usec max_latency=48usec max_latency_slot=487.12 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 max_crc_delay=3.5ms max_ce_delay=3ms max_pucch_harq_delay=3.5ms avg_prach_delay=n/a
2025-11-11T15:34:42.525618 [METRICS ] Scheduler UE pci=9 rnti=0x4602 metrics: cqi=10 dl_ri=2.6 dl_mcs=13 dl_brate=144kbps dl_nof_ok=133 dl_nof_nok=462 dl_error_rate=77% dl_bs=119 dl_nof_prbs=2099 pusch_snr_db=31.1 pusch_rsrp_db=-0.3 ul_ri=1 ul_mcs=28 ul_brate=4.35kbps ul_nof_ok=1 ul_nof_nok=26 ul_error_rate=96% ul_nof_prbs=156 bsr=0 sr_count=5 f0f1_invalid_harqs=230 f2f3f4_invalid_harqs=0 f2f3f4_invalid_csis=33 pusch_invalid_harqs=0 pusch_invalid_csis=0 ta=302ns srs_ta=n/a last_phr=-32 avg_ul_ce_delay=3ms max_ul_ce_delay=3ms avg_crc_delay=3.04ms max_crc_delay=3.5ms avg_pusch_harq_delay=n/a max_pusch_harq_delay=n/a avg_pucch_harq_delay=3ms max_pucch_harq_delay=3.5ms
2025-11-11T15:34:42.525631 [METRICS ] OFH sector#0 pci=9 received messages stats: rx_total=31400 rx_early=0 rx_on_time=31348 rx_late=52; ether_rx: cpu_usage=0.7% max_latency=1.82us avg_latency=0.23us throughput=1659.62Mbps rx_bytes=207244800; ether_tx: cpu_usage=2.8% max_latency=2.21us avg_latency=0.91us throughput=1625.80Mbps tx_bytes=203021824; rcv_prach: cpu_usage=0.6% max_latency=22.76us avg_latency=1.20us; rcv_ul: cpu_usage=18.0% max_latency=36.00us avg_latency=6.75us; tx_dl_up: cpu_usage=11.1% dl_up_max_latency=156.19us dl_up_avg_latency=46.35us; tx_dl_cp: cpu_usage=0.1% dl_cp_max_latency=9.20us dl_cp_avg_latency=0.49us; tx_ul_cp: cpu_usage=0.1% ul_cp_max_latency=8.29us ul_cp_avg_latency=0.33us; message_tx: cpu_usage=4.6% max_latency=10.58us avg_latency=1.65us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-11T15:34:43.525545 [METRICS ] MAC cell pci=9 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=1 wall_clock_latency=[avg=11usec max=55usec max_slot=582.2] dl_tti_req_latency=[avg=5usec max=52usec max_slot=582.2] tx_data_req_latency=[avg=0usec max=4usec max_slot=624.1] ul_tti_req_latency=[avg=5usec max=20usec max_slot=652.6] slot_ind_latency=[avg=13usec max=47usec max_slot=591.18]
2025-11-11T15:34:43.525573 [METRICS ] Scheduler cell pci=9 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=600 nof_ul_slots=1400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0.08 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_
Here is a sample picture of deployment. Here RU9 (in red) is the ceiling mounted RU 550 and UE(in green) are sitting on a table on the floor. The UEs would be 3 to 4 meters from the RU.
Can you please share your working config for Benetel RAN550-1v1.4.1-NM-25fa970 4x4 MIMO and latest SRS RAN ? I tried several configurations and parameters but it didn't help.
Any feedback on this ?
I'm still struggling to make it work.
RU Power:
root@benetelru:~# TXMeanPower
TX 1 Mean Power: 14.9578 dBm
TX 2 Mean Power: -13.7984 dBm
TX 3 Mean Power: 7.48982 dBm
TX 4 Mean Power: 4.16011 dBm
root@benetelru:~#
RRU Config:
# Config file for Benetel RANx50 radio units
# Please place this file in /etc
# Please make sure that parameter values are modified after the = sign without any other format changes
# MIMO mode - the radio can operate in 1_3, 2_4, 1_2_3_4_4x2 or 1_2_3_4_4x4 mode
# For uncompressed mode use only 2x2 configuration (1_2 or 2_4)
# Variable name : mimo_mode
# Valid options : 1_3
# 2_4
# 1_2_3_4_4x2
# 1_2_3_4_4x4
mimo_mode=1_2_3_4_4x4
# FPGA downlink scaling in steps of 6 dB (0, 6, 12 and 18 can be set)
# Variable name : downlink_scaling
# Valid options : 0
# 6
# 12
# 18
downlink_scaling=0
# PRACH format
# Variable name : prach_format
# Valid options : short
# long
prach_format=short
# PRACH frequncy offset dynamic (C-plane Type 3 freqOffset field) / static (using ru_config.cfg file)
# Dynamic LF PRACH is currently not supported
# Static SF PRACH is curently not supported
# Variable name : prach_freq_offset_dynamic
# Valid options : true
# false
prach_freq_offset_dynamic=true
# PRACH frequncy offset (in steps of one half the subcarrier spacings delta_f_Hz) for static configuration
# Currently supported for static LF PRACH configuration only.
# Variable name : prach_freq_offset
# Valid options : +-2*freq_offset_Hz/delta_f_Hz
prach_freq_offset=0
# O-RU Compression settings (note uncompressed mode is not supported when RU is in 4x2 or 4x4 mode)
# Variable name : compression
# Valid options : static_uncompressed
# dynamic_uncompressed
# static_compressed
# dynamic_compressed
compression=dynamic_compressed
# Prach msg1 frequency start. Static (using ru_config.cfg file)
# Currently supported only for LF PRACH static configuration only.
# SF prach msg1FreqStart will read from C-Plane sectionType3 message
# Variable name : prach_msg1_freq_start
# Valid options : 0
# max = 270 (depending on PRACH format and bandwidth)
prach_msg1_freq_start=0
# Long form PRACH compression settings
# Variable name : lf_prach_compression_enable
# Valid options : true
# false
lf_prach_compression_enable=true
# C-Plane per-symbol workaround
# Variable name : cplane_per_symbol_workaround
# Valid options : enabled
# disabled
cplane_per_symbol_workaround=disabled
# CUPLANE dl couplling sectionID
# Variable name : cuplane_dl_coupling_sectionI
# Valid options : enabled
# disabled
cuplane_dl_coupling_sectionID=disabled
# # FlexRAN PRACH workaround (uncompressed PRACH w/ udCompHdr)
# Variable name : flexran_prach_workaround
# Valid options : enabled
# disabled
flexran_prach_workaround=disabled
# DPD reset timer
# Variable name : dpd_reset_timer
# Valid options : Time between DPD resets in seconds, eg. 43200 for 12 hours
dpd_reset_timer=43200
# C-Plane DU MAC address
# Variable name : c_plane_du_mac
# Valid options : A valid MAC address separated by semicolons eg. 00:11:22:33:44:67
c_plane_du_mac=00:11:22:33:14:6e
# U-Plane DU MAC address
# Variable name : u_plane_du_mac
# Valid options : A valid MAC address separated by semicolons eg. 00:11:22:33:44:66
u_plane_du_mac=00:11:22:33:14:6e
# DU VLAN tag control information for uplink U-Plane traffic
# Variable name : u_plane_du_vlan_uplink
# Valid options : Hex number from 1 to fff
u_plane_du_vlan_uplink=14
# DU VLAN tag control information for downlink U-Plane traffic
# Variable name : u_plane_du_vlan_downlink
# Valid options : Hex number from 1 to fff
u_plane_du_vlan_downlink=14
# DU VLAN tag control information for C-Plane traffic
# Variable name : c_plane_du_vlan
# Valid options : Hex number from 1 to fff
c_plane_du_vlan=14
# TDD switching
# Variable name : tdd_switching
# Valid options : Contact Benetel support if changes needed
tdd_switching=1500
# RU bandwidth in Hz
# Variable name : bandwidth_hz
# Valid options : 10000000
# 20000000
# 40000000
# 50000000
# 60000000
# 80000000
# 90000000
# 100000000
bandwidth_hz=100000000
# RU centre frequency in Hz
# Variable name : centre_frequency_hz
# Valid options : check frequency range in /tmp/logs/ru_information
centre_frequency_hz=4000020000
# RU Tx power in dBm
# Variable name : tx_power_dbm
# Valid options : check max output power in /tmp/logs/ru_information or User Guide.
# Range varies between (max output power -20) and max output power
tx_power_dbm=20.000000
# Configuration of TDD pattern
# Variable name : tdd_pattern_1
# tdd_pattern_2
# Valid options : Maximum ten slots total, only characters D, S & U, all uppercase, must begin with Downlink slot and contain one or no Special slot.
# Please refer to User Guide for configurations of the required TDD pattern.
tdd_pattern_1=DDDD
tdd_pattern_2=DDDSUU
# This is UL heavy TDD slots
#tdd_pattern_1=DDSU
#tdd_pattern_2=UUUUUU
# Configuration of TDD special slots for TDD patterns (tdd_pattern_1, tdd_pattern_2)
# Variable name : special_slots_symbols
# special_slots_symbols1
# special_slots_symbols2
# Valid options : 14 symbols must be specified, only characters D (Downlink), G (Guard) and
# U (Uplink), all uppercase, must begin with Downlink.
#
# special_slots_symbols is a common configuration for both special slots
# located in tdd_pattern_1 or tdd_pattern_2.
#
# special_slots_symbols_1 corresponds to special slot in tdd_pattern_1.
# special_slots_symbols_2 corresponds to special slot in tdd_pattern_2.
# special_slots_symbols[1/2] parameters overwrite common configuration
# specified by special_slots_symbols.
# Please refer to User Guide for configurations of the required special slot pattern.
special_slots_symbols=DDDDDDGGGGUUUU
#special_slots_symbols=DDDDDGGGGUUUUU
# Configure below only when two special slots need to be configured using different symbol patterns
special_slots_symbols1=
special_slots_symbols2=
# LF PRACH SlotID_Flag
# Variable name : lf_prach_slot_id
# Valid options : 0 (LF Prach U-Plane packet Slot Id 0)
# 1 (LF Prach U-Plane packet Slot Id 1)
lf_prach_slot_id=0
# DL_special slot tunning (Internal use)
# Variable name : dl_tuning_special_slot
# Valid range : 0x0:0x13bc
dl_tuning_special_slot=0x13b6
# Configuration of FH C-plane timing reference point defined by ORAN specification
# Variable name : cplane_per_symbol_timing
# Valid options : false - C-plane per slot timing
# (C-plane timing reference point is a slot boundary where corresponding U-plane packets are transmitted)
# true - C-plane per symbol timing
# (C-plane timing reference point is the first corresponding U-plane symbol boundary)
# If not specified, default is false.
cplane_per_symbol_timing=false
# Fix for issues related to non-ideal timing in certain network/synchronization deployment scenarios (eg. C4)
# Variable name : non_ideal_c4_timing_enable
# Valid options : true
# false
non_ideal_c4_timing_enable=false
# Configure M-Plane array carriers activation behavior to align with v16.01 specification
# Variable name : m_plane_u_plane_config_v16
# Valid options : true
# false
m_plane_u_plane_config_v16=false
Here is my config:
cell_cfg:
band: 77
nof_antennas_dl: 4
nof_antennas_ul: 4
common_scs: 30
prach:
prach_config_index: 159
prach_frequency_start: 12
prach_root_sequence_index: 1
zero_correlation_zone: 0
pusch:
mcs_table: qam64
olla_target_bler: 0.10
p0_nominal_with_grant: -86
min_k2: 2
ssb:
ssb_block_power_dbm: -16
ssb_period: 20
pucch:
sr_period_ms: 80
pdsch:
mcs_table: qam256
olla_target_bler: 0.05
dc_offset: center
csi:
csi_rs_period: 10
tdd_ul_dl_cfg:
dl_ul_tx_period: 10
nof_dl_slots: 7
nof_dl_symbols: 6
nof_ul_slots: 2
nof_ul_symbols: 4
ru_ofh:
t1a_max_cp_dl: 535
t1a_min_cp_dl: 286
t1a_max_cp_ul: 535
t1a_min_cp_ul: 286
t1a_max_up: 390
t1a_min_up: 80
ta4_max: 500
ta4_min: 25
is_prach_cp_enabled: true
compr_method_ul: bfp
compr_bitwidth_ul: 9
compr_method_dl: bfp
compr_bitwidth_dl: 9
compr_method_prach: bfp
compr_bitwidth_prach: 9
enable_ul_static_compr_hdr: false
enable_dl_static_compr_hdr: false
# iq_scaling: 5.5
ru_reference_level_dBFS: -12
subcarrier_rms_backoff_dB: 0
metrics:
autostart_stdout_metrics: true
enable_log: true
layers:
enable_ru: true
SRS logs:
Cell pci=20, bw=100 MHz, 4T4R, dl_arfcn=666668 (n77), dl_freq=4000.02 MHz, dl_ssb_arfcn=663936, ul_freq=4000.02 MHz
N2: Connection to AMF on 192.168.101.16:38412 completed
==== gNB started ===
Type <h> to view help
|--------------------DL---------------------|-------------------------UL----------------------------------
pci rnti | cqi ri mcs brate ok nok (%) dl_bs | pusch rsrp ri mcs brate ok nok (%) bsr ta phr
20 4601 | 14 1.0 8 2.8k 3 1 25% 0 | 27.9 -7.3 1 9 4.22k 1 0 0% 0 -195n 24
20 4601 | 13 1.0 2 2.1k 8 0 0% 0 | 26.8 -6.1 1 28 47.7k 12 0 0% 0 -214n 26
20 4601 | n/a n/a 0 0 0 0 0% 0 | n/a n/a 1 0 0 0 0 0% 0 42n 26
20 4602 | 15 1.0 5 3.9k 8 1 11% 0 | 31.6 -5.0 1 26 43.2k 11 0 0% 0 2n 30
20 4602 | 12 1.0 2 1.0k 3 0 0% 0 | 35.0 -4.6 1 28 8.70k 2 0 0% 0 11n 27
20 4602 | 15 3.0 0 0 0 0 0% 0 | n/a n/a 1 0 0 0 0 0% 0 43n 27
Logs:
ved messages stats: rx_total=4800 rx_early=0 rx_on_time=4800 rx_late=0; ether_rx: cpu_usage=0.5% max_latency=1.85us avg_latency=1.00us throughput=14.45Mbps rx_bytes=1804800; ether_tx: cpu_usage=2.0% max_latency=1.91us avg_latency=0.91us throughput=1227.03Mbps tx_bytes=153225216; rcv_prach: cpu_usage=0.6% max_latency=21.05us avg_latency=1.32us; rcv_ul: cpu_usage=0.0% max_latency=0.00us avg_latency=0.00us; tx_dl_up: cpu_usage=8.3% dl_up_max_latency=152.62us dl_up_avg_latency=58.34us; tx_dl_cp: cpu_usage=0.1% dl_cp_max_latency=1.25us dl_cp_avg_latency=0.42us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=1.13us ul_cp_avg_latency=0.29us; message_tx: cpu_usage=4.0% max_latency=8.72us avg_latency=1.43us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-25T12:21:38.284545 [METRICS ] MAC cell pci=20 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=9usec max=27usec max_slot=208.1] dl_tti_req_latency=[avg=8usec max=24usec max_slot=208.1] tx_data_req_latency=[avg=0usec max=3usec max_slot=272.1] ul_tti_req_latency=[avg=1usec max=11usec max_slot=269.19] slot_ind_latency=[avg=13usec max=48usec max_slot=228.6]
2025-11-25T12:21:38.284571 [METRICS ] Scheduler cell pci=20 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=1600 nof_ul_slots=400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=0 mean_latency=6usec max_latency=22usec max_latency_slot=271.6 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a
2025-11-25T12:21:38.284585 [METRICS ] OFH sector#0 pci=20 received messages stats: rx_total=4800 rx_early=0 rx_on_time=4800 rx_late=0; ether_rx: cpu_usage=0.5% max_latency=1.89us avg_latency=0.99us throughput=14.47Mbps rx_bytes=1804800; ether_tx: cpu_usage=2.0% max_latency=2.01us avg_latency=0.91us throughput=1228.26Mbps tx_bytes=153225216; rcv_prach: cpu_usage=0.6% max_latency=30.28us avg_latency=1.34us; rcv_ul: cpu_usage=0.0% max_latency=0.00us avg_latency=0.00us; tx_dl_up: cpu_usage=8.4% dl_up_max_latency=152.16us dl_up_avg_latency=59.14us; tx_dl_cp: cpu_usage=0.1% dl_cp_max_latency=1.13us dl_cp_avg_latency=0.44us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=1.24us ul_cp_avg_latency=0.32us; message_tx: cpu_usage=4.1% max_latency=9.35us avg_latency=1.45us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-25T12:21:39.284570 [METRICS ] MAC cell pci=20 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=9usec max=28usec max_slot=336.1] dl_tti_req_latency=[avg=8usec max=25usec max_slot=336.1] tx_data_req_latency=[avg=0usec max=3usec max_slot=336.1] ul_tti_req_latency=[avg=1usec max=12usec max_slot=389.18] slot_ind_latency=[avg=13usec max=45usec max_slot=365.8]
2025-11-25T12:21:39.284595 [METRICS ] Scheduler cell pci=20 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=1600 nof_ul_slots=400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=0 mean_latency=6usec max_latency=17usec max_latency_slot=367.6 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a
2025-11-25T12:21:39.284609 [METRICS ] OFH sector#0 pci=20 received messages stats: rx_total=4800 rx_early=0 rx_on_time=4800 rx_late=0; ether_rx: cpu_usage=0.5% max_latency=0.82us avg_latency=0.99us throughput=14.44Mbps rx_bytes=1804800; ether_tx: cpu_usage=2.0% max_latency=1.92us avg_latency=0.90us throughput=1229.24Mbps tx_bytes=153655552; rcv_prach: cpu_usage=0.6% max_latency=13.29us avg_latency=1.32us; rcv_ul: cpu_usage=0.0% max_latency=0.00us avg_latency=0.00us; tx_dl_up: cpu_usage=8.4% dl_up_max_latency=154.85us dl_up_avg_latency=58.85us; tx_dl_cp: cpu_usage=0.1% dl_cp_max_latency=8.63us dl_cp_avg_latency=0.44us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=2.63us ul_cp_avg_latency=0.30us; message_tx: cpu_usage=4.0% max_latency=9.24us avg_latency=1.43us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-25T12:21:40.285550 [METRICS ] MAC cell pci=20 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=9usec max=27usec max_slot=496.1] dl_tti_req_latency=[avg=8usec max=24usec max_slot=416.1] tx_data_req_latency=[avg=0usec max=5usec max_slot=496.1] ul_tti_req_latency=[avg=1usec max=10usec max_slot=498.19] slot_ind_latency=[avg=14usec max=45usec max_slot=475.1]
2025-11-25T12:21:40.285577 [METRICS ] Scheduler cell pci=20 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=1600 nof_ul_slots=400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=0 mean_latency=6usec max_latency=17usec max_latency_slot=450.17 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a
2025-11-25T12:21:40.285592 [METRICS ] OFH sector#0 pci=20 received messages stats: rx_total=4800 rx_early=0 rx_on_time=4800 rx_late=0; ether_rx: cpu_usage=0.5% max_latency=0.52us avg_latency=1.00us throughput=14.44Mbps rx_bytes=1804800; ether_tx: cpu_usage=2.0% max_latency=2.00us avg_latency=0.91us throughput=1225.80Mbps tx_bytes=153225216; rcv_prach: cpu_usage=0.6% max_latency=24.43us avg_latency=1.33us; rcv_ul: cpu_usage=0.0% max_latency=0.00us avg_latency=0.00us; tx_dl_up: cpu_usage=8.3% dl_up_max_latency=143.49us dl_up_avg_latency=58.25us; tx_dl_cp: cpu_usage=0.1% dl_cp_max_latency=1.09us dl_cp_avg_latency=0.43us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=2.77us ul_cp_avg_latency=0.29us; message_tx: cpu_usage=4.0% max_latency=9.86us avg_latency=1.44us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-25T12:21:41.285541 [METRICS ] MAC cell pci=20 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=9usec max=23usec max_slot=544.1] dl_tti_req_latency=[avg=8usec max=21usec max_slot=544.1] tx_data_req_latency=[avg=0usec max=2usec max_slot=528.1] ul_tti_req_latency=[avg=1usec max=10usec max_slot=548.19] slot_ind_latency=[avg=14usec max=47usec max_slot=582.3]
2025-11-25T12:21:41.285580 [METRICS ] Scheduler cell pci=20 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=1600 nof_ul_slots=400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=0 mean_latency=6usec max_latency=16usec max_latency_slot=506.7 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a
2025-11-25T12:21:41.285596 [METRICS ] OFH sector#0 pci=20 received messages stats: rx_total=4800 rx_early=0 rx_on_time=4800 rx_late=0; ether_rx: cpu_usage=0.5% max_latency=0.52us avg_latency=0.99us throughput=14.45Mbps rx_bytes=1804800; ether_tx: cpu_usage=2.0% max_latency=1.87us avg_latency=0.92us throughput=1227.03Mbps tx_bytes=153225216; rcv_prach: cpu_usage=0.6% max_latency=22.10us avg_latency=1.32us; rcv_ul: cpu_usage=0.0% max_latency=0.00us avg_latency=0.00us; tx_dl_up: cpu_usage=8.3% dl_up_max_latency=126.89us dl_up_avg_latency=58.14us; tx_dl_cp: cpu_usage=0.1% dl_cp_max_latency=8.71us dl_cp_avg_latency=0.43us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=0.85us ul_cp_avg_latency=0.28us; message_tx: cpu_usage=4.1% max_latency=9.64us avg_latency=1.45us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-25T12:21:42.285551 [METRICS ] MAC cell pci=20 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=9usec max=25usec max_slot=688.1] dl_tti_req_latency=[avg=8usec max=23usec max_slot=688.1] tx_data_req_latency=[avg=0usec max=3usec max_slot=672.1] ul_tti_req_latency=[avg=1usec max=13usec max_slot=674.19] slot_ind_latency=[avg=14usec max=46usec max_slot=636.6]
2025-11-25T12:21:42.285587 [METRICS ] Scheduler cell pci=20 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=1600 nof_ul_slots=400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=0 mean_latency=6usec max_latency=16usec max_latency_slot=604.6 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a
2025-11-25T12:21:42.285601 [METRICS ] OFH sector#0 pci=20 received messages stats: rx_total=4800 rx_early=0 rx_on_time=4800 rx_late=0; ether_rx: cpu_usage=0.5% max_latency=0.78us avg_latency=0.99us throughput=14.44Mbps rx_bytes=1804800; ether_tx: cpu_usage=2.0% max_latency=1.90us avg_latency=0.92us throughput=1225.80Mbps tx_bytes=153225216; rcv_prach: cpu_usage=0.6% max_latency=16.54us avg_latency=1.34us; rcv_ul: cpu_usage=0.0% max_latency=0.00us avg_latency=0.00us; tx_dl_up: cpu_usage=8.4% dl_up_max_latency=137.60us dl_up_avg_latency=58.88us; tx_dl_cp: cpu_usage=0.1% dl_cp_max_latency=2.87us dl_cp_avg_latency=0.44us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=2.73us ul_cp_avg_latency=0.31us; message_tx: cpu_usage=4.0% max_latency=8.71us avg_latency=1.44us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-25T12:21:43.285591 [METRICS ] MAC cell pci=20 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=10usec max=54usec max_slot=785.5] dl_tti_req_latency=[avg=8usec max=46usec max_slot=785.5] tx_data_req_latency=[avg=0usec max=11usec max_slot=782.5] ul_tti_req_latency=[avg=1usec max=28usec max_slot=774.8] slot_ind_latency=[avg=14usec max=46usec max_slot=770.16]
2025-11-25T12:21:43.285602 [METRICS ] Scheduler cell pci=20 metrics: total_dl_brate=3.00kbps total_ul_brate=43.0kbps nof_prbs=273 nof_dl_slots=1600 nof_ul_slots=400 nof_prach_preambles=1 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0.00563 puschs_per_slot=0.03 failed_pdcch=0 failed_uci=0 nof_ues=1 mean_latency=6usec max_latency=34usec max_latency_slot=785.5 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=1 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 max_crc_delay=3ms max_ce_delay=3ms max_pucch_harq_delay=3ms avg_prach_delay=7ms events=[{rnti=0x4602 slot=774.7 type=ue_create}, {rnti=0x4602 slot=777.7 type=ue_reconf}]
2025-11-25T12:21:43.285612 [METRICS ] Scheduler UE pci=20 rnti=0x4602 metrics: cqi=15 dl_ri=1.0 dl_mcs=5 dl_brate=3.93kbps dl_nof_ok=8 dl_nof_nok=1 dl_error_rate=11% dl_bs=0 dl_nof_prbs=76 dl_olla=0 pusch_snr_db=31.6 pusch_rsrp_db=-5.0 ul_ri=1 ul_mcs=26 ul_brate=43.2kbps ul_nof_ok=11 ul_nof_nok=0 ul_error_rate=0% ul_nof_prbs=77 bsr=0 sr_count=3 f0f1_invalid_harqs=0 f2f3f4_invalid_harqs=0 f2f3f4_invalid_csis=1 pusch_invalid_harqs=0 pusch_invalid_csis=0 ul_olla=0 ta=-23ns srs_ta=n/a last_phr=30 avg_ul_ce_delay=3ms max_ul_ce_delay=3ms avg_crc_delay=3ms max_crc_delay=3ms avg_pusch_harq_delay=n/a max_pusch_harq_delay=n/a avg_pucch_harq_delay=3ms max_pucch_harq_delay=3ms
2025-11-25T12:21:43.285621 [METRICS ] OFH sector#0 pci=20 received messages stats: rx_total=7656 rx_early=0 rx_on_time=7656 rx_late=0; ether_rx: cpu_usage=0.5% max_latency=1.15us avg_latency=0.67us throughput=190.10Mbps rx_bytes=23738880; ether_tx: cpu_usage=2.1% max_latency=1.89us avg_latency=0.91us throughput=1291.14Mbps tx_bytes=161231104; rcv_prach: cpu_usage=0.6% max_latency=16.43us avg_latency=1.30us; rcv_ul: cpu_usage=2.0% max_latency=33.28us avg_latency=6.87us; tx_dl_up: cpu_usage=8.8% dl_up_max_latency=127.85us dl_up_avg_latency=58.46us; tx_dl_cp: cpu_usage=0.1% dl_cp_max_latency=1.54us dl_cp_avg_latency=0.44us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=3.13us ul_cp_avg_latency=0.30us; message_tx: cpu_usage=4.2% max_latency=9.11us avg_latency=1.49us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-25T12:21:44.285589 [METRICS ] MAC cell pci=20 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=10usec max=35usec max_slot=809.11] dl_tti_req_latency=[avg=8usec max=34usec max_slot=816.16] tx_data_req_latency=[avg=0usec max=12usec max_slot=809.11] ul_tti_req_latency=[avg=1usec max=14usec max_slot=877.8] slot_ind_latency=[avg=13usec max=44usec max_slot=805.1]
2025-11-25T12:21:44.285600 [METRICS ] Scheduler cell pci=20 metrics: total_dl_brate=1.00kbps total_ul_brate=8.00kbps nof_prbs=273 nof_dl_slots=1600 nof_ul_slots=400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0.00187 puschs_per_slot=0.005 failed_pdcch=0 failed_uci=0 nof_ues=1 mean_latency=6usec max_latency=24usec max_latency_slot=816.16 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 max_crc_delay=3ms max_ce_delay=3.5ms max_pucch_harq_delay=3ms avg_prach_delay=n/a
2025-11-25T12:21:44.285613 [METRICS ] Scheduler UE pci=20 rnti=0x4602 metrics: cqi=12 dl_ri=1.0 dl_mcs=2 dl_brate=1.00kbps dl_nof_ok=3 dl_nof_nok=0 dl_error_rate=0% dl_bs=0 dl_nof_prbs=22 dl_olla=0 pusch_snr_db=35.0 pusch_rsrp_db=-4.6 ul_ri=1 ul_mcs=28 ul_brate=8.70kbps ul_nof_ok=2 ul_nof_nok=0 ul_error_rate=0% ul_nof_prbs=12 bsr=0 sr_count=2 f0f1_invalid_harqs=0 f2f3f4_invalid_harqs=0 f2f3f4_invalid_csis=82 pusch_invalid_harqs=0 pusch_invalid_csis=0 ul_olla=0 ta=18ns srs_ta=n/a last_phr=27 avg_ul_ce_delay=3.25ms max_ul_ce_delay=3.5ms avg_crc_delay=3ms max_crc_delay=3ms avg_pusch_harq_delay=n/a max_pusch_harq_delay=n/a avg_pucch_harq_delay=3ms max_pucch_harq_delay=3ms
2025-11-25T12:21:44.285626 [METRICS ] OFH sector#0 pci=20 received messages stats: rx_total=11296 rx_early=0 rx_on_time=11296 rx_late=0; ether_rx: cpu_usage=0.6% max_latency=1.06us avg_latency=0.50us throughput=413.55Mbps rx_bytes=51694080; ether_tx: cpu_usage=2.0% max_latency=3.10us avg_latency=0.90us throughput=1243.25Mbps tx_bytes=155406592; rcv_prach: cpu_usage=0.6% max_latency=18.23us avg_latency=1.32us; rcv_ul: cpu_usage=4.4% max_latency=20.83us avg_latency=6.85us; tx_dl_up: cpu_usage=8.5% dl_up_max_latency=142.05us dl_up_avg_latency=58.73us; tx_dl_cp: cpu_usage=0.1% dl_cp_max_latency=1.32us dl_cp_avg_latency=0.44us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=2.57us ul_cp_avg_latency=0.29us; message_tx: cpu_usage=4.1% max_latency=13.41us avg_latency=1.46us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-25T12:21:44.844489 [DU-MNG ] [W] ue=0: RLF detected with cause="MAC max KOs reached". Timer of 1000 msec to release UE started...
2025-11-25T12:21:45.285576 [METRICS ] MAC cell pci=20 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=10usec max=24usec max_slot=912.1] dl_tti_req_latency=[avg=8usec max=21usec max_slot=912.1] tx_data_req_latency=[avg=0usec max=2usec max_slot=976.1] ul_tti_req_latency=[avg=1usec max=12usec max_slot=935.8] slot_ind_latency=[avg=13usec max=45usec max_slot=967.6]
2025-11-25T12:21:45.285585 [METRICS ] Scheduler cell pci=20 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=1600 nof_ul_slots=400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=1 mean_latency=6usec max_latency=18usec max_latency_slot=927.6 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a
2025-11-25T12:21:45.285595 [METRICS ] Scheduler UE pci=20 rnti=0x4602 metrics: cqi=15 dl_ri=3.0 dl_mcs=0 dl_brate=0bps dl_nof_ok=0 dl_nof_nok=0 dl_error_rate=0% dl_bs=0 dl_nof_prbs=0 dl_olla=0 pusch_snr_db=n/a pusch_rsrp_db=n/a ul_ri=1 ul_mcs=0 ul_brate=0bps ul_nof_ok=0 ul_nof_nok=0 ul_error_rate=0% ul_nof_prbs=0 bsr=0 sr_count=0 f0f1_invalid_harqs=0 f2f3f4_invalid_harqs=0 f2f3f4_invalid_csis=99 pusch_invalid_harqs=0 pusch_invalid_csis=0 ul_olla=0 ta=43ns srs_ta=n/a last_phr=27 avg_ul_ce_delay=n/a max_ul_ce_delay=n/a avg_crc_delay=n/a max_crc_delay=n/a avg_pusch_harq_delay=n/a max_pusch_harq_delay=n/a avg_pucch_harq_delay=n/a max_pucch_harq_delay=n/a
2025-11-25T12:21:45.285606 [METRICS ] OFH sector#0 pci=20 received messages stats: rx_total=11128 rx_early=0 rx_on_time=11128 rx_late=0; ether_rx: cpu_usage=0.6% max_latency=1.14us avg_latency=0.50us throughput=403.63Mbps rx_bytes=50403840; ether_tx: cpu_usage=2.0% max_latency=1.77us avg_latency=0.90us throughput=1227.26Mbps tx_bytes=153254144; rcv_prach: cpu_usage=0.6% max_latency=11.92us avg_latency=1.33us; rcv_ul: cpu_usage=4.3% max_latency=26.26us avg_latency=6.86us; tx_dl_up: cpu_usage=8.4% dl_up_max_latency=148.68us dl_up_avg_latency=59.12us; tx_dl_cp: cpu_usage=0.1% dl_cp_max_latency=3.25us dl_cp_avg_latency=0.44us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=3.01us ul_cp_avg_latency=0.31us; message_tx: cpu_usage=4.1% max_latency=8.90us avg_latency=1.45us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-25T12:21:46.285543 [METRICS ] MAC cell pci=20 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=10usec max=59usec max_slot=32.13] dl_tti_req_latency=[avg=8usec max=46usec max_slot=32.13] tx_data_req_latency=[avg=0usec max=11usec max_slot=32.13] ul_tti_req_latency=[avg=1usec max=18usec max_slot=40.9] slot_ind_latency=[avg=13usec max=46usec max_slot=7.1]
2025-11-25T12:21:46.285569 [METRICS ] Scheduler cell pci=20 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=1600 nof_ul_slots=400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0.00875 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=0 mean_latency=6usec max_latency=26usec max_latency_slot=32.13 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a events=[{rnti=0x4602 slot=46.4 type=ue_rem}]
2025-11-25T12:21:46.285583 [METRICS ] OFH sector#0 pci=20 received messages stats: rx_total=9840 rx_early=0 rx_on_time=9840 rx_late=0; ether_rx: cpu_usage=0.5% max_latency=0.67us avg_latency=0.55us throughput=324.10Mbps rx_bytes=40512000; ether_tx: cpu_usage=2.1% max_latency=2.19us avg_latency=0.91us throughput=1274.18Mbps tx_bytes=159272960; rcv_prach: cpu_usage=0.6% max_latency=19.91us avg_latency=1.32us; rcv_ul: cpu_usage=3.5% max_latency=30.12us avg_latency=6.87us; tx_dl_up: cpu_usage=8.6% dl_up_max_latency=131.15us dl_up_avg_latency=58.34us; tx_dl_cp: cpu_usage=0.1% dl_cp_max_latency=1.39us dl_cp_avg_latency=0.44us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=1.30us ul_cp_avg_latency=0.29us; message_tx: cpu_usage=4.2% max_latency=10.83us avg_latency=1.48us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-25T12:21:47.285588 [METRICS ] MAC cell pci=20 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=9usec max=25usec max_slot=80.1] dl_tti_req_latency=[avg=8usec max=23usec max_slot=80.1] tx_data_req_latency=[avg=0usec max=3usec max_slot=128.1] ul_tti_req_latency=[avg=1usec max=11usec max_slot=141.9] slot_ind_latency=[avg=14usec max=48usec max_slot=131.19]
2025-11-25T12:21:47.285612 [METRICS ] Scheduler cell pci=20 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=1600 nof_ul_slots=400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=0 mean_latency=6usec max_latency=18usec max_latency_slot=151.17 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a
2025-11-25T12:21:47.285626 [METRICS ] OFH sector#0 pci=20 received messages stats: rx_total=4800 rx_early=0 rx_on_time=4800 rx_late=0; ether_rx: cpu_usage=0.5% max_latency=0.55us avg_latency=0.99us throughput=14.44Mbps rx_bytes=1804800; ether_tx: cpu_usage=2.0% max_latency=1.45us avg_latency=0.91us throughput=1229.24Mbps tx_bytes=153655552; rcv_prach: cpu_usage=0.6% max_latency=15.59us avg_latency=1.34us; rcv_ul: cpu_usage=0.0% max_latency=0.00us avg_latency=0.00us; tx_dl_up: cpu_usage=8.4% dl_up_max_latency=153.39us dl_up_avg_latency=58.84us; tx_dl_cp: cpu_usage=0.1% dl_cp_max_latency=3.19us dl_cp_avg_latency=0.44us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=2.66us ul_cp_avg_latency=0.30us; message_tx: cpu_usage=4.0% max_latency=7.54us avg_latency=1.44us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-25T12:21:48.285592 [METRICS ] MAC cell pci=20 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=9usec max=22usec max_slot=208.1] dl_tti_req_latency=[avg=8usec max=20usec max_slot=208.1] tx_data_req_latency=[avg=0usec max=2usec max_slot=240.1] ul_tti_req_latency=[avg=1usec max=11usec max_slot=234.19] slot_ind_latency=[avg=14usec max=47usec max_slot=263.0]
2025-11-25T12:21:48.285629 [METRICS ] Scheduler cell pci=20 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=1600 nof_ul_slots=400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=0 mean_latency=6usec max_latency=16usec max_latency_slot=242.16 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a
2025-11-25T12:21:48.285641 [METRICS ] OFH sector#0 pci=20 received messages stats: rx_total=4800 rx_early=0 rx_on_time=4800 rx_late=0; ether_rx: cpu_usage=0.5% max_latency=1.57us avg_latency=1.00us throughput=14.45Mbps rx_bytes=1804800; ether_tx: cpu_usage=2.0% max_latency=2.08us avg_latency=0.91us throughput=1227.03Mbps tx_bytes=153225216; rcv_prach: cpu_usage=0.6% max_latency=11.22us avg_latency=1.30us; rcv_ul: cpu_usage=0.0% max_latency=0.00us avg_latency=0.00us; tx_dl_up: cpu_usage=8.2% dl_up_max_latency=143.55us dl_up_avg_latency=57.84us; tx_dl_cp: cpu_usage=0.1% dl_cp_max_latency=7.52us dl_cp_avg_latency=0.44us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=2.50us ul_cp_avg_latency=0.29us; message_tx: cpu_usage=4.0% max_latency=9.91us avg_latency=1.44us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-25T12:21:49.285572 [METRICS ] MAC cell pci=20 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_switches=0 nof_involuntary_context_switches=0 wall_clock_latency=[avg=9usec max=25usec max_slot=304.1] dl_tti_req_latency=[avg=8usec max=23usec max_slot=304.1] tx_data_req_latency=[avg=0usec max=2usec max_slot=336.1] ul_tti_req_latency=[avg=1usec max=12usec max_slot=306.19] slot_ind_latency=[avg=14usec max=47usec max_slot=332.13]
2025-11-25T12:21:49.285600 [METRICS ] Scheduler cell pci=20 metrics: total_dl_brate= 0.0bps total_ul_brate= 0.0bps nof_prbs=273 nof_dl_slots=1600 nof_ul_slots=400 nof_prach_preambles=0 error_indications=0 pdsch_rbs_per_slot=0 pusch_rbs_per_slot=0 pdschs_per_slot=0 puschs_per_slot=0 failed_pdcch=0 failed_uci=0 nof_ues=0 mean_latency=6usec max_latency=17usec max_latency_slot=287.6 latency_hist=[2000, 0, 0, 0, 0, 0, 0, 0, 0, 0] msg3_ok=0 msg3_nok=0 late_dl_harqs=0 late_ul_harqs=0 avg_prach_delay=n/a
2025-11-25T12:21:49.285614 [METRICS ] OFH sector#0 pci=20 received messages stats: rx_total=4800 rx_early=0 rx_on_time=4800 rx_late=0; ether_rx: cpu_usage=0.5% max_latency=2.15us avg_latency=0.99us throughput=14.45Mbps rx_bytes=1804800; ether_tx: cpu_usage=2.0% max_latency=1.70us avg_latency=0.92us throughput=1227.03Mbps tx_bytes=153225216; rcv_prach: cpu_usage=0.6% max_latency=17.45us avg_latency=1.32us; rcv_ul: cpu_usage=0.0% max_latency=0.00us avg_latency=0.00us; tx_dl_up: cpu_usage=8.3% dl_up_max_latency=139.25us dl_up_avg_latency=58.15us; tx_dl_cp: cpu_usage=0.1% dl_cp_max_latency=8.05us dl_cp_avg_latency=0.43us; tx_ul_cp: cpu_usage=0.0% ul_cp_max_latency=1.10us ul_cp_avg_latency=0.29us; message_tx: cpu_usage=4.0% max_latency=7.93us avg_latency=1.44us; tx_kpis: nof_late_dl_grids=0 nof_late_ul_req=0
2025-11-25T12:21:50.285542 [METRICS ] MAC cell pci=20 metrics: nof_slots=2000 slot_duration=500usec nof_voluntary_context_sw^C
Hi,
I am having the same problem, sometimes I can see the cell on the UE but it does not register, also, the TX Mean Power of Antenna 2 is much lower than the other ones, just like yours.
Have you find any solution to this?
Hi @antonioo420 , not really. I'm still struggling with it. Sometimes I'm able to see the cell and attach but its not reliable. Still waiting for SRS team to share some light on this.