angelo

@dlech Pushed new PR: - fix custom register names - split backend and dac backend commits - add comments where possible

> > Documentation talks about "AD3552R IP core". How can AD3552R be common to other DAC's in the future ? I am assuming that other XXX IP cores will use...

Hi @dlech @nunojsa , sorry for the many things to be fixed, code was just in a rough shape. I checked now return values everywhere. I hope now the code...

- fixed points above where/as possible, please see my comments - samplerate returned always as per buffered mode (DDR) as 33333333 UPS - TODO: eventually remove totally ext_sync stuff

New push, fixed bad sine wave output due to wrong enable/disable DDR sequence. DDR must be set on DAC and DAC chip accordingly, in the proper sequence. Also, EXT_SYNC mechanism...