Adrian Sampson

Wahoo; thank you for summarizing! Just capturing the synchronous discussion a little bit, on this point: > Does not generate an output JSON compatible with our testing infrastructure I had...

Interesting point about the Verilog implementation… I guess the overall question is: do we need to eliminate all 0-bit signals before emitting Verilog? (That is, does Verilog (or do common...

Looks great. One minor thing we've talked about here is the thought that we could run a primitive-free program after the "PC" step. It is of course really hard to...

That makes sense! Too bad it's not easier to write a primitive-free program. Maybe we have to forge ahead and get registers or something working before we have a v0...

The Hip New Way to do this kind of thing is to use the WebAssembly component model and [jco][]! If anyone's interested, overhauling the build pipeline to use that could...

That validation thing seems like a pretty good idea! It would hopefully be pretty straightforward to check that the list of passes actually exists. And you're right that including all...

Thanks for sketching this up, @calebmkim. To take your discussion one step farther (envisioning what this would look like with the much-maligned "general `with`" statement)… first, correct me if I'm...

Yeah, you're absolutely right about wasting another cycle to set the special 1-bit register to 0. And it's a good idea to special-case the one-invocation case to avoid needing this…...

Indeed; this is a good observation about the (compiler optimization) reason that the dynamic version of Calyx exists: by giving the programmer fewer guarantees, it lets the compiler make stronger...

Really good points here. To summarize, we believe it is possible for the compiler to provide zero-cycle transitions in `seq { a ; b }` when it can be certain...