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Published 20 hours ago • verified publisher icon rust-embedded-community

RISC-V targets do not support ARM "thread mode" check

Open Disasm opened this issue 5 years ago • 0 comments

https://github.com/rust-embedded-community/async-on-embedded/blob/47eb470ec53fd88035faa5360c0167f3987304c8/async-embedded/src/executor.rs#L203-L207

This code checks for a value of the VECTACTIVE field (only for bits 7..0 of the 9-bit field). This value corresponds to the current interrupt number handled (0 for none).

I wonder what should we use here for RISC-V. @ilya-epifanov any ideas?

Disasm avatar Jun 21 '20 05:06 Disasm