Why is there core timer?

[luojia65]

I found this name in both patches/gd32vf103.yaml and generated pac crate. The User Manual provided by GigaDevice (I have its version 1.2) have not documented on a peripheral called ctimer.

Is this provided by the chip but not documented? Or is this peripheral wrapped from RISC-V's core CSR configurations? I need to know why we apply this patch. Thanks!

[Disasm]

This peripheral wasn't in GD32VF103.svd for some reason, but it does exist in a chip. It's a core peripheral and documented in "Bumblebee core datasheet" and not "User manual".

[luojia65]

Thanks! I'll check them out :)