Rachit Nigam comments

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                                            Rachit Nigam

Parallel assignment asserts do not work with icarus verilog

One possible fix to this is using `===` which allows checking whether a value is `'x` or not. We can generate the following conditional: ``` if (g1 !== 'x &...

Sharing: Allow larger units to replace smaller ones

@calebmkim's study of sharing behavior has revealed that this is probably a bad idea. Closing this for now

Generate compact control

This was done thanks to @calebmkim's effort on the static paper!

AXI returns unexpected 0s

Reopening this! @zzy666666zzy we were all traveling last week so can look into this a bit more now that we’re back.

[Calyx] Generate non-combinational reads for memories

Fixed by #396

`mult_pipe` not inferred correctly pipelined for DSP inference

Might be interested to @andrewb1999 too

`mult_pipe` not inferred correctly pipelined for DSP inference

Weirdly, even a Filament generated design seems to have this problem? Would be useful to figure out what behavioral RTL would generate the correct code or if we need to...

`mult_pipe` not inferred correctly pipelined for DSP inference

Wow, that’s crazy. This would indicate we should switch our mult implementation to be 4 cycles. Also, @andrewb1999 and I discussed the possibility to using the mult latency insensitive interface...

`mult_pipe` not inferred correctly pipelined for DSP inference

Wow, that’s crazy. This would indicate we should switch our mult implementation to be 4 cycles. Also, @andrewb1999 and I discussed the possibility to using the mult latency insensitive interface...

Axi test harness

Okay, my changes should fix the silly `fud` problem @nathanielnrn was running into. Once this is merged, we should check off tasks in #1104 and create a new issue to...