Test failures in Vector Mask Instructions

[ghost]

Test failures in Vector Mask Instructions

Last updated: November 21, 2022

Description:

Tests for the unit testing have been added and necessary environment changes have been made to run the tests on Spike and ARA. Following tests are found to be failing on the RTL. The tests can be verified by running on Spike using the usual Make targets in ara/apps (usingmake riscv_tests_spike)

In this issue, vector mask instructions related failure have been reported. Other tests are also available. Each of these combination is a test file in ara/apps/riscv-tests/isa/rv64uv/ and is also listed in its Makefrag.

vmand

Failing:

vmand.mm_LMUL1SEW32
vmand.mm_LMUL1SEW64
vmand.mm_LMUL2SEW32
vmand.mm_LMUL2SEW64
vmand.mm_LMUL4SEW32
vmand.mm_LMUL4SEW64
vmand.mm_LMUL8SEW64

Hanging:

vmand.mm_LMUL1SEW16
vmand.mm_LMUL2SEW16
vmand.mm_LMUL4SEW16
vmand.mm_LMUL8SEW16
vmand.mm_LMUL8SEW32

vmandn

Failing:

vmandn.mm_LMUL1SEW32
vmandn.mm_LMUL2SEW32
vmandn.mm_LMUL4SEW32
vmandn.mm_LMUL4SEW64
vmandn.mm_LMUL8SEW64

Hanging:

vmandn.mm_LMUL1SEW16
vmandn.mm_LMUL1SEW64
vmandn.mm_LMUL2SEW16
vmandn.mm_LMUL2SEW64
vmandn.mm_LMUL4SEW16
vmandn.mm_LMUL8SEW16
vmandn.mm_LMUL8SEW32

vmnand

Failing:

vmnand.mm_LMUL1SEW32
vmnand.mm_LMUL1SEW64
vmnand.mm_LMUL1SEW8
vmnand.mm_LMUL2SEW16
vmnand.mm_LMUL2SEW32
vmnand.mm_LMUL2SEW64
vmnand.mm_LMUL2SEW8
vmnand.mm_LMUL4SEW16
vmnand.mm_LMUL4SEW32
vmnand.mm_LMUL4SEW64
vmnand.mm_LMUL4SEW8
vmnand.mm_LMUL8SEW64
vmnand.mm_LMUL8SEW8

Hanging:

vmnand.mm_LMUL1SEW16
vmnand.mm_LMUL8SEW16
vmnand.mm_LMUL8SEW32

vmnor

Failing:

vmnor.mm_LMUL1SEW32
vmnor.mm_LMUL1SEW64
vmnor.mm_LMUL1SEW8
vmnor.mm_LMUL2SEW16
vmnor.mm_LMUL2SEW32
vmnor.mm_LMUL2SEW64
vmnor.mm_LMUL2SEW8
vmnor.mm_LMUL4SEW16
vmnor.mm_LMUL4SEW32
vmnor.mm_LMUL4SEW64
vmnor.mm_LMUL4SEW8
vmnor.mm_LMUL8SEW64
vmnor.mm_LMUL8SEW8

Hanging:

vmnor.mm_LMUL1SEW16
vmnor.mm_LMUL8SEW16
vmnor.mm_LMUL8SEW32

vmor

Failing:

vmor.mm_LMUL1SEW32
vmor.mm_LMUL1SEW64
vmor.mm_LMUL2SEW32
vmor.mm_LMUL2SEW64
vmor.mm_LMUL4SEW32
vmor.mm_LMUL4SEW64
vmor.mm_LMUL8SEW64

Hanging:

vmor.mm_LMUL1SEW16
vmor.mm_LMUL2SEW16
vmor.mm_LMUL4SEW16
vmor.mm_LMUL8SEW16
vmor.mm_LMUL8SEW32

vmorn

Failing:

vmorn.mm_LMUL1SEW32
vmorn.mm_LMUL1SEW64
vmorn.mm_LMUL1SEW8
vmorn.mm_LMUL2SEW16
vmorn.mm_LMUL2SEW32
vmorn.mm_LMUL2SEW64
vmorn.mm_LMUL2SEW8
vmorn.mm_LMUL4SEW16
vmorn.mm_LMUL4SEW32
vmorn.mm_LMUL4SEW64
vmorn.mm_LMUL4SEW8
vmorn.mm_LMUL8SEW64
vmorn.mm_LMUL8SEW8

Hanging:

vmorn.mm_LMUL1SEW16
vmorn.mm_LMUL8SEW16
vmorn.mm_LMUL8SEW32

vmxnor

Failing:

vmxnor.mm_LMUL1SEW32
vmxnor.mm_LMUL1SEW64
vmxnor.mm_LMUL1SEW8
vmxnor.mm_LMUL2SEW16
vmxnor.mm_LMUL2SEW32
vmxnor.mm_LMUL2SEW64
vmxnor.mm_LMUL2SEW8
vmxnor.mm_LMUL4SEW16
vmxnor.mm_LMUL4SEW32
vmxnor.mm_LMUL4SEW64
vmxnor.mm_LMUL4SEW8
vmxnor.mm_LMUL8SEW64
vmxnor.mm_LMUL8SEW8

Hanging:

vmxnor.mm_LMUL1SEW16
vmxnor.mm_LMUL8SEW16
vmxnor.mm_LMUL8SEW32

vmxor

Failing:

vmxor.mm_LMUL1SEW32
vmxor.mm_LMUL1SEW64
vmxor.mm_LMUL2SEW32
vmxor.mm_LMUL2SEW64
vmxor.mm_LMUL4SEW32
vmxor.mm_LMUL4SEW64
vmxor.mm_LMUL8SEW64

Hanging:

vmxor.mm_LMUL1SEW16
vmxor.mm_LMUL2SEW16
vmxor.mm_LMUL4SEW16
vmxor.mm_LMUL8SEW16
vmxor.mm_LMUL8SEW32

vcpop

Failing:

vcpop.m_LMUL1SEW16
vcpop.m_LMUL1SEW32
vcpop.m_LMUL1SEW8
vcpop.m_LMUL2SEW16
vcpop.m_LMUL2SEW32
vcpop.m_LMUL2SEW8
vcpop.m_LMUL4SEW16
vcpop.m_LMUL4SEW32
vcpop.m_LMUL4SEW64
vcpop.m_LMUL4SEW8
vcpop.m_LMUL8SEW16
vcpop.m_LMUL8SEW32
vcpop.m_LMUL8SEW64
vcpop.m_LMUL8SEW8

vfirst

Failing:

vfirst.m_LMUL1SEW16
vfirst.m_LMUL1SEW32
vfirst.m_LMUL1SEW64
vfirst.m_LMUL1SEW8
vfirst.m_LMUL2SEW16
vfirst.m_LMUL2SEW32
vfirst.m_LMUL2SEW64
vfirst.m_LMUL2SEW8
vfirst.m_LMUL4SEW16
vfirst.m_LMUL4SEW32
vfirst.m_LMUL4SEW64
vfirst.m_LMUL4SEW8
vfirst.m_LMUL8SEW16
vfirst.m_LMUL8SEW32
vfirst.m_LMUL8SEW64
vfirst.m_LMUL8SEW8

vmsbf

Failing:

vmsbf.m_LMUL1SEW16
vmsbf.m_LMUL1SEW32
vmsbf.m_LMUL1SEW64
vmsbf.m_LMUL1SEW8
vmsbf.m_LMUL2SEW16
vmsbf.m_LMUL2SEW32
vmsbf.m_LMUL2SEW64
vmsbf.m_LMUL2SEW8
vmsbf.m_LMUL4SEW16
vmsbf.m_LMUL4SEW32
vmsbf.m_LMUL4SEW64
vmsbf.m_LMUL4SEW8
vmsbf.m_LMUL8SEW16
vmsbf.m_LMUL8SEW32
vmsbf.m_LMUL8SEW64
vmsbf.m_LMUL8SEW8

vmsif

Failing:

vmsif.m_LMUL1SEW16
vmsif.m_LMUL1SEW32
vmsif.m_LMUL1SEW64
vmsif.m_LMUL1SEW8
vmsif.m_LMUL2SEW16
vmsif.m_LMUL2SEW32
vmsif.m_LMUL2SEW64
vmsif.m_LMUL2SEW8
vmsif.m_LMUL4SEW16
vmsif.m_LMUL4SEW32
vmsif.m_LMUL4SEW64
vmsif.m_LMUL4SEW8
vmsif.m_LMUL8SEW16
vmsif.m_LMUL8SEW32
vmsif.m_LMUL8SEW64
vmsif.m_LMUL8SEW8

viota

Failing:

viota.m_LMUL1SEW16
viota.m_LMUL1SEW32
viota.m_LMUL1SEW64
viota.m_LMUL1SEW8
viota.m_LMUL2SEW16
viota.m_LMUL2SEW32
viota.m_LMUL2SEW64
viota.m_LMUL2SEW8
viota.m_LMUL4SEW16
viota.m_LMUL4SEW32
viota.m_LMUL4SEW64
viota.m_LMUL4SEW8
viota.m_LMUL8SEW16
viota.m_LMUL8SEW32
viota.m_LMUL8SEW64
viota.m_LMUL8SEW8

Verification branch: main_verif_10x

Steps to recreate this issue:

1. git clone https://github.com/pulp-platform/ara.git
2. git remote add test_repo "https://github.com/10x-Engineers/ara"
3. git fetch test_repo
4. git checkout main_verif_10x
5. cd apps
6. make riscv_tests
7. cd ../hardware
8. make simv app="name of individual ELF" or make riscv_tests_simv -j4 to run regression

[ghost]

Issue updated with failing/hanging status of available tests.