Test failures in Vector Integer Arithmetic Instructions

[ghost]

Test failures in Vector Integer Arithmetic Instructions

Last updated: November 13, 2022

Description:

Tests for the unit testing have been added and necessary environment changes have been made to run the tests on Spike and ARA. Following tests are found to be failing on the RTL. The tests can be verified by running on Spike using the usual Make targets in ara/apps (usingmake riscv_tests_spike)

In this issue, vector integer arithmetic instructions related failure have been reported. Other tests are also available. Each of these combination is a test file in ara/apps/riscv-tests/isa/rv64uv/ and is also listed in its Makefrag.

Failing tests:

VDIV

Failing:

vdiv.vv_LMUL1SEW16
vdiv.vv_LMUL1SEW32
vdiv.vv_LMUL1SEW64
vdiv.vv_LMUL1SEW8
vdiv.vv_LMUL2SEW16
vdiv.vv_LMUL2SEW32
vdiv.vv_LMUL2SEW64
vdiv.vv_LMUL2SEW8
vdiv.vv_LMUL4SEW16
vdiv.vv_LMUL4SEW32
vdiv.vv_LMUL4SEW64
vdiv.vv_LMUL4SEW8
vdiv.vv_LMUL8SEW16
vdiv.vv_LMUL8SEW32
vdiv.vv_LMUL8SEW64
vdiv.vv_LMUL8SEW8
vdiv.vx_LMUL1SEW16
vdiv.vx_LMUL1SEW32
vdiv.vx_LMUL1SEW64
vdiv.vx_LMUL1SEW8
vdiv.vx_LMUL2SEW16
vdiv.vx_LMUL2SEW32
vdiv.vx_LMUL2SEW64
vdiv.vx_LMUL2SEW8
vdiv.vx_LMUL4SEW16
vdiv.vx_LMUL4SEW32
vdiv.vx_LMUL4SEW64
vdiv.vx_LMUL4SEW8
vdiv.vx_LMUL8SEW16
vdiv.vx_LMUL8SEW32
vdiv.vx_LMUL8SEW64
vdiv.vx_LMUL8SEW8

VDIVU

Failing:

vdivu.vv_LMUL1SEW8
vdivu.vv_LMUL2SEW16
vdivu.vv_LMUL2SEW8
vdivu.vv_LMUL4SEW16
vdivu.vv_LMUL4SEW32
vdivu.vv_LMUL4SEW8
vdivu.vv_LMUL8SEW16
vdivu.vv_LMUL8SEW32
vdivu.vv_LMUL8SEW64
vdivu.vv_LMUL8SEW8

Hanging:

vdivu.vv_LMUL1SEW16
vdivu.vv_LMUL1SEW32
vdivu.vv_LMUL1SEW64
vdivu.vv_LMUL2SEW32
vdivu.vv_LMUL2SEW64
vdivu.vv_LMUL4SEW64
vdivu.vx_LMUL1SEW16
vdivu.vx_LMUL1SEW32
vdivu.vx_LMUL1SEW64
vdivu.vx_LMUL1SEW8
vdivu.vx_LMUL2SEW16
vdivu.vx_LMUL2SEW32
vdivu.vx_LMUL2SEW64
vdivu.vx_LMUL2SEW8
vdivu.vx_LMUL4SEW16
vdivu.vx_LMUL4SEW32
vdivu.vx_LMUL4SEW64
vdivu.vx_LMUL4SEW8
vdivu.vx_LMUL8SEW16
vdivu.vx_LMUL8SEW32
vdivu.vx_LMUL8SEW64
vdivu.vx_LMUL8SEW8

VREM

Failing:

vrem.vv_LMUL1SEW16
vrem.vv_LMUL1SEW32
vrem.vv_LMUL1SEW64
vrem.vv_LMUL1SEW8
vrem.vv_LMUL2SEW16
vrem.vv_LMUL2SEW32
vrem.vv_LMUL2SEW64
vrem.vv_LMUL2SEW8
vrem.vv_LMUL4SEW16
vrem.vv_LMUL4SEW32
vrem.vv_LMUL4SEW64
vrem.vv_LMUL4SEW8
vrem.vv_LMUL8SEW16
vrem.vv_LMUL8SEW32
vrem.vv_LMUL8SEW64
vrem.vv_LMUL8SEW8
vrem.vx_LMUL1SEW16
vrem.vx_LMUL1SEW32
vrem.vx_LMUL1SEW64
vrem.vx_LMUL1SEW8
vrem.vx_LMUL2SEW16
vrem.vx_LMUL2SEW32
vrem.vx_LMUL2SEW64
vrem.vx_LMUL2SEW8
vrem.vx_LMUL4SEW16
vrem.vx_LMUL4SEW32
vrem.vx_LMUL4SEW64
vrem.vx_LMUL4SEW8
vrem.vx_LMUL8SEW16
vrem.vx_LMUL8SEW32
vrem.vx_LMUL8SEW64
vrem.vx_LMUL8SEW8

VREMU

Failing:

vremu.vv_LMUL1SEW8
vremu.vv_LMUL2SEW16
vremu.vv_LMUL2SEW8
vremu.vv_LMUL4SEW16
vremu.vv_LMUL4SEW32
vremu.vv_LMUL4SEW8
vremu.vv_LMUL8SEW16
vremu.vv_LMUL8SEW32
vremu.vv_LMUL8SEW64
vremu.vv_LMUL8SEW8
vremu.vx_LMUL1SEW8
vremu.vx_LMUL2SEW16
vremu.vx_LMUL2SEW8
vremu.vx_LMUL4SEW16
vremu.vx_LMUL4SEW32
vremu.vx_LMUL4SEW8
vremu.vx_LMUL8SEW16
vremu.vx_LMUL8SEW32
vremu.vx_LMUL8SEW64
vremu.vx_LMUL8SEW8

Hanging:

vremu.vv_LMUL1SEW16
vremu.vv_LMUL1SEW32
vremu.vv_LMUL1SEW64
vremu.vv_LMUL2SEW32
vremu.vv_LMUL2SEW64
vremu.vv_LMUL4SEW64
vremu.vx_LMUL1SEW16
vremu.vx_LMUL1SEW32
vremu.vx_LMUL1SEW64
vremu.vx_LMUL2SEW32
vremu.vx_LMUL2SEW64
vremu.vx_LMUL4SEW64

VMSGT

Failing:

vmsgt.vi_LMUL1SEW16
vmsgt.vi_LMUL1SEW32
vmsgt.vi_LMUL1SEW64
vmsgt.vi_LMUL1SEW8
vmsgt.vi_LMUL2SEW16
vmsgt.vi_LMUL2SEW32
vmsgt.vi_LMUL2SEW64
vmsgt.vi_LMUL2SEW8
vmsgt.vi_LMUL4SEW16
vmsgt.vi_LMUL4SEW32
vmsgt.vi_LMUL4SEW64
vmsgt.vi_LMUL8SEW32
vmsgt.vi_LMUL8SEW64
vmsgt.vx_LMUL1SEW16
vmsgt.vx_LMUL1SEW32
vmsgt.vx_LMUL1SEW64
vmsgt.vx_LMUL1SEW8
vmsgt.vx_LMUL2SEW16
vmsgt.vx_LMUL2SEW32
vmsgt.vx_LMUL2SEW64
vmsgt.vx_LMUL2SEW8
vmsgt.vx_LMUL4SEW16
vmsgt.vx_LMUL4SEW32
vmsgt.vx_LMUL4SEW64
vmsgt.vx_LMUL8SEW32
vmsgt.vx_LMUL8SEW64

Hanging:

vmsgt.vi_LMUL4SEW8
vmsgt.vi_LMUL8SEW16
vmsgt.vi_LMUL8SEW8
vmsgt.vx_LMUL4SEW8
vmsgt.vx_LMUL8SEW16
vmsgt.vx_LMUL8SEW8

VMSGTU

Failing:

vmsgtu.vi_LMUL1SEW16
vmsgtu.vi_LMUL1SEW32
vmsgtu.vi_LMUL1SEW64
vmsgtu.vi_LMUL1SEW8
vmsgtu.vi_LMUL2SEW16
vmsgtu.vi_LMUL2SEW32
vmsgtu.vi_LMUL2SEW64
vmsgtu.vi_LMUL2SEW8
vmsgtu.vi_LMUL4SEW16
vmsgtu.vi_LMUL4SEW32
vmsgtu.vi_LMUL4SEW64
vmsgtu.vi_LMUL8SEW32
vmsgtu.vi_LMUL8SEW64
vmsgtu.vx_LMUL1SEW16
vmsgtu.vx_LMUL1SEW32
vmsgtu.vx_LMUL1SEW64
vmsgtu.vx_LMUL1SEW8
vmsgtu.vx_LMUL2SEW16
vmsgtu.vx_LMUL2SEW32
vmsgtu.vx_LMUL2SEW64
vmsgtu.vx_LMUL2SEW8
vmsgtu.vx_LMUL4SEW16
vmsgtu.vx_LMUL4SEW32
vmsgtu.vx_LMUL4SEW64
vmsgtu.vx_LMUL8SEW32
vmsgtu.vx_LMUL8SEW64

Hanging:

vmsgtu.vi_LMUL4SEW8
vmsgtu.vi_LMUL8SEW16
vmsgtu.vi_LMUL8SEW8
vmsgtu.vx_LMUL4SEW8
vmsgtu.vx_LMUL8SEW16
vmsgtu.vx_LMUL8SEW8

VMSNE

Failing:

vmsne.vi_LMUL1SEW16
vmsne.vi_LMUL1SEW32
vmsne.vi_LMUL1SEW64
vmsne.vi_LMUL1SEW8
vmsne.vi_LMUL2SEW16
vmsne.vi_LMUL2SEW32
vmsne.vi_LMUL2SEW64
vmsne.vi_LMUL2SEW8
vmsne.vi_LMUL4SEW16
vmsne.vi_LMUL4SEW32
vmsne.vi_LMUL4SEW64
vmsne.vi_LMUL8SEW32
vmsne.vi_LMUL8SEW64
vmsne.vv_LMUL1SEW16
vmsne.vv_LMUL1SEW32
vmsne.vv_LMUL1SEW64
vmsne.vv_LMUL1SEW8
vmsne.vv_LMUL2SEW16
vmsne.vv_LMUL2SEW32
vmsne.vv_LMUL2SEW64
vmsne.vv_LMUL2SEW8
vmsne.vv_LMUL4SEW16
vmsne.vv_LMUL4SEW32
vmsne.vv_LMUL4SEW64
vmsne.vv_LMUL8SEW32
vmsne.vv_LMUL8SEW64
vmsne.vx_LMUL1SEW16
vmsne.vx_LMUL1SEW32
vmsne.vx_LMUL1SEW64
vmsne.vx_LMUL1SEW8
vmsne.vx_LMUL2SEW16
vmsne.vx_LMUL2SEW32
vmsne.vx_LMUL2SEW64
vmsne.vx_LMUL2SEW8
vmsne.vx_LMUL4SEW16
vmsne.vx_LMUL4SEW32
vmsne.vx_LMUL4SEW64
vmsne.vx_LMUL8SEW32
vmsne.vx_LMUL8SEW64

Hanging:

vmsne.vx_LMUL8SEW8
vmsne.vi_LMUL4SEW8
vmsne.vi_LMUL8SEW16
vmsne.vx_LMUL4SEW8
vmsne.vx_LMUL8SEW16
vmsne.vv_LMUL4SEW8
vmsne.vv_LMUL8SEW16
vmsne.vv_LMUL8SEW8
vmsne.vi_LMUL8SEW8

VMADC

Failing:

vmadc.vi_LMUL2SEW16
vmadc.vi_LMUL2SEW32
vmadc.vi_LMUL2SEW64
vmadc.vi_LMUL2SEW8
vmadc.vi_LMUL4SEW16
vmadc.vi_LMUL4SEW32
vmadc.vi_LMUL4SEW64
vmadc.vi_LMUL4SEW8
vmadc.vi_LMUL8SEW16
vmadc.vi_LMUL8SEW32
vmadc.vi_LMUL8SEW64
vmadc.vi_LMUL8SEW8
vmadc.vim_LMUL1SEW8
vmadc.vim_LMUL2SEW16
vmadc.vim_LMUL2SEW32
vmadc.vim_LMUL2SEW64
vmadc.vim_LMUL2SEW8
vmadc.vim_LMUL4SEW16
vmadc.vim_LMUL4SEW32
vmadc.vim_LMUL4SEW64
vmadc.vim_LMUL4SEW8
vmadc.vim_LMUL8SEW16
vmadc.vim_LMUL8SEW32
vmadc.vim_LMUL8SEW64
vmadc.vim_LMUL8SEW8
vmadc.vv_LMUL2SEW16
vmadc.vv_LMUL2SEW32
vmadc.vv_LMUL2SEW64
vmadc.vv_LMUL2SEW8
vmadc.vv_LMUL4SEW16
vmadc.vv_LMUL4SEW32
vmadc.vv_LMUL4SEW64
vmadc.vv_LMUL4SEW8
vmadc.vv_LMUL8SEW16
vmadc.vv_LMUL8SEW32
vmadc.vv_LMUL8SEW64
vmadc.vv_LMUL8SEW8
vmadc.vvm_LMUL1SEW8
vmadc.vvm_LMUL2SEW16
vmadc.vvm_LMUL2SEW32
vmadc.vvm_LMUL2SEW64
vmadc.vvm_LMUL2SEW8
vmadc.vvm_LMUL4SEW16
vmadc.vvm_LMUL4SEW32
vmadc.vvm_LMUL4SEW64
vmadc.vvm_LMUL4SEW8
vmadc.vvm_LMUL8SEW16
vmadc.vvm_LMUL8SEW32
vmadc.vvm_LMUL8SEW64
vmadc.vvm_LMUL8SEW8
vmadc.vx_LMUL2SEW16
vmadc.vx_LMUL2SEW32
vmadc.vx_LMUL2SEW64
vmadc.vx_LMUL2SEW8
vmadc.vx_LMUL4SEW16
vmadc.vx_LMUL4SEW32
vmadc.vx_LMUL4SEW64
vmadc.vx_LMUL4SEW8
vmadc.vx_LMUL8SEW16
vmadc.vx_LMUL8SEW32
vmadc.vx_LMUL8SEW64
vmadc.vx_LMUL8SEW8
vmadc.vxm_LMUL1SEW8
vmadc.vxm_LMUL2SEW16
vmadc.vxm_LMUL2SEW32
vmadc.vxm_LMUL2SEW64
vmadc.vxm_LMUL2SEW8
vmadc.vxm_LMUL4SEW16
vmadc.vxm_LMUL4SEW32
vmadc.vxm_LMUL4SEW64
vmadc.vxm_LMUL4SEW8
vmadc.vxm_LMUL8SEW16
vmadc.vxm_LMUL8SEW32
vmadc.vxm_LMUL8SEW64
vmadc.vxm_LMUL8SEW8

Hanging:

vmadc.vxm_LMUL1SEW16
vmadc.vxm_LMUL1SEW32
vmadc.vxm_LMUL1SEW64
vmadc.vx_LMUL1SEW16
vmadc.vx_LMUL1SEW32
vmadc.vx_LMUL1SEW64
vmadc.vx_LMUL1SEW8
vmadc.vvm_LMUL1SEW16
vmadc.vvm_LMUL1SEW32
vmadc.vvm_LMUL1SEW64
vmadc.vv_LMUL1SEW16
vmadc.vv_LMUL1SEW32
vmadc.vv_LMUL1SEW64
vmadc.vv_LMUL1SEW8
vmadc.vim_LMUL1SEW16
vmadc.vim_LMUL1SEW32
vmadc.vim_LMUL1SEW64
vmadc.vi_LMUL1SEW16
vmadc.vi_LMUL1SEW32
vmadc.vi_LMUL1SEW64
vmadc.vi_LMUL1SEW8

VMSBC

Failing:

vmsbc.vv_LMUL2SEW16
vmsbc.vv_LMUL2SEW32
vmsbc.vv_LMUL2SEW64
vmsbc.vv_LMUL2SEW8
vmsbc.vv_LMUL4SEW16
vmsbc.vv_LMUL4SEW32
vmsbc.vv_LMUL4SEW64
vmsbc.vv_LMUL4SEW8
vmsbc.vv_LMUL8SEW16
vmsbc.vv_LMUL8SEW32
vmsbc.vv_LMUL8SEW64
vmsbc.vv_LMUL8SEW8
vmsbc.vvm_LMUL1SEW8
vmsbc.vvm_LMUL2SEW16
vmsbc.vvm_LMUL2SEW32
vmsbc.vvm_LMUL2SEW64
vmsbc.vvm_LMUL2SEW8
vmsbc.vvm_LMUL4SEW16
vmsbc.vvm_LMUL4SEW32
vmsbc.vvm_LMUL4SEW64
vmsbc.vvm_LMUL4SEW8
vmsbc.vvm_LMUL8SEW16
vmsbc.vvm_LMUL8SEW32
vmsbc.vvm_LMUL8SEW64
vmsbc.vvm_LMUL8SEW8
vmsbc.vx_LMUL1SEW8
vmsbc.vx_LMUL2SEW16
vmsbc.vx_LMUL2SEW32
vmsbc.vx_LMUL2SEW64
vmsbc.vx_LMUL2SEW8
vmsbc.vx_LMUL4SEW16
vmsbc.vx_LMUL4SEW32
vmsbc.vx_LMUL4SEW64
vmsbc.vx_LMUL4SEW8
vmsbc.vx_LMUL8SEW16
vmsbc.vx_LMUL8SEW32
vmsbc.vx_LMUL8SEW64
vmsbc.vx_LMUL8SEW8
vmsbc.vxm_LMUL1SEW8
vmsbc.vxm_LMUL2SEW16
vmsbc.vxm_LMUL2SEW32
vmsbc.vxm_LMUL2SEW64
vmsbc.vxm_LMUL2SEW8
vmsbc.vxm_LMUL4SEW16
vmsbc.vxm_LMUL4SEW32
vmsbc.vxm_LMUL4SEW64
vmsbc.vxm_LMUL4SEW8
vmsbc.vxm_LMUL8SEW16
vmsbc.vxm_LMUL8SEW32
vmsbc.vxm_LMUL8SEW64
vmsbc.vxm_LMUL8SEW8

Hanging:

vmsbc.vv_LMUL1SEW16
vmsbc.vv_LMUL1SEW32
vmsbc.vv_LMUL1SEW64
vmsbc.vv_LMUL1SEW8
vmsbc.vvm_LMUL1SEW16
vmsbc.vvm_LMUL1SEW32
vmsbc.vvm_LMUL1SEW64
vmsbc.vx_LMUL1SEW16
vmsbc.vx_LMUL1SEW32
vmsbc.vx_LMUL1SEW64
vmsbc.vxm_LMUL1SEW16
vmsbc.vxm_LMUL1SEW32
vmsbc.vxm_LMUL1SEW64

VMSEQ

Failing:

vmseq.vi_LMUL1SEW16
vmseq.vi_LMUL1SEW32
vmseq.vi_LMUL1SEW64
vmseq.vi_LMUL1SEW8
vmseq.vi_LMUL2SEW16
vmseq.vi_LMUL2SEW32
vmseq.vi_LMUL2SEW64
vmseq.vi_LMUL2SEW8
vmseq.vi_LMUL4SEW16
vmseq.vi_LMUL4SEW32
vmseq.vi_LMUL4SEW64
vmseq.vi_LMUL8SEW32
vmseq.vi_LMUL8SEW64
vmseq.vv_LMUL1SEW16
vmseq.vv_LMUL1SEW32
vmseq.vv_LMUL1SEW64
vmseq.vv_LMUL1SEW8
vmseq.vv_LMUL2SEW16
vmseq.vv_LMUL2SEW32
vmseq.vv_LMUL2SEW64
vmseq.vv_LMUL2SEW8
vmseq.vv_LMUL4SEW16
vmseq.vv_LMUL4SEW32
vmseq.vv_LMUL4SEW64
vmseq.vv_LMUL8SEW32
vmseq.vv_LMUL8SEW64
vmseq.vx_LMUL1SEW16
vmseq.vx_LMUL1SEW32
vmseq.vx_LMUL1SEW64
vmseq.vx_LMUL1SEW8
vmseq.vx_LMUL2SEW16
vmseq.vx_LMUL2SEW32
vmseq.vx_LMUL2SEW64
vmseq.vx_LMUL2SEW8
vmseq.vx_LMUL4SEW16
vmseq.vx_LMUL4SEW32
vmseq.vx_LMUL4SEW64
vmseq.vx_LMUL8SEW32
vmseq.vx_LMUL8SEW64

Hanging:

vmseq.vi_LMUL4SEW8
vmseq.vi_LMUL8SEW16
vmseq.vi_LMUL8SEW8
vmseq.vv_LMUL4SEW8
vmseq.vv_LMUL8SEW16
vmseq.vv_LMUL8SEW8
vmseq.vx_LMUL4SEW8
vmseq.vx_LMUL8SEW16
vmseq.vx_LMUL8SEW8

VMSLE

Failing:

vmsle.vi_LMUL1SEW16
vmsle.vi_LMUL1SEW32
vmsle.vi_LMUL1SEW64
vmsle.vi_LMUL1SEW8
vmsle.vi_LMUL2SEW16
vmsle.vi_LMUL2SEW32
vmsle.vi_LMUL2SEW64
vmsle.vi_LMUL2SEW8
vmsle.vi_LMUL4SEW16
vmsle.vi_LMUL4SEW32
vmsle.vi_LMUL4SEW64
vmsle.vi_LMUL8SEW32
vmsle.vi_LMUL8SEW64
vmsle.vv_LMUL1SEW16
vmsle.vv_LMUL1SEW32
vmsle.vv_LMUL1SEW64
vmsle.vv_LMUL1SEW8
vmsle.vv_LMUL2SEW16
vmsle.vv_LMUL2SEW32
vmsle.vv_LMUL2SEW64
vmsle.vv_LMUL2SEW8
vmsle.vv_LMUL4SEW16
vmsle.vv_LMUL4SEW32
vmsle.vv_LMUL4SEW64
vmsle.vv_LMUL8SEW32
vmsle.vv_LMUL8SEW64
vmsle.vx_LMUL1SEW16
vmsle.vx_LMUL1SEW32
vmsle.vx_LMUL1SEW64
vmsle.vx_LMUL1SEW8
vmsle.vx_LMUL2SEW16
vmsle.vx_LMUL2SEW32
vmsle.vx_LMUL2SEW64
vmsle.vx_LMUL2SEW8
vmsle.vx_LMUL4SEW16
vmsle.vx_LMUL4SEW32
vmsle.vx_LMUL4SEW64
vmsle.vx_LMUL8SEW32
vmsle.vx_LMUL8SEW64

Hanging:

vmsle.vi_LMUL4SEW8
vmsle.vi_LMUL8SEW16
vmsle.vi_LMUL8SEW8
vmsle.vv_LMUL4SEW8
vmsle.vv_LMUL8SEW16
vmsle.vv_LMUL8SEW8
vmsle.vx_LMUL4SEW8
vmsle.vx_LMUL8SEW16
vmsle.vx_LMUL8SEW8

VMSLEU

Failing:

vmsleu.vi_LMUL1SEW16
vmsleu.vi_LMUL1SEW32
vmsleu.vi_LMUL1SEW64
vmsleu.vi_LMUL1SEW8
vmsleu.vi_LMUL2SEW16
vmsleu.vi_LMUL2SEW32
vmsleu.vi_LMUL2SEW64
vmsleu.vi_LMUL2SEW8
vmsleu.vi_LMUL4SEW16
vmsleu.vi_LMUL4SEW32
vmsleu.vi_LMUL4SEW64
vmsleu.vi_LMUL8SEW32
vmsleu.vi_LMUL8SEW64
vmsleu.vv_LMUL1SEW16
vmsleu.vv_LMUL1SEW32
vmsleu.vv_LMUL1SEW64
vmsleu.vv_LMUL1SEW8
vmsleu.vv_LMUL2SEW16
vmsleu.vv_LMUL2SEW32
vmsleu.vv_LMUL2SEW64
vmsleu.vv_LMUL2SEW8
vmsleu.vv_LMUL4SEW16
vmsleu.vv_LMUL4SEW32
vmsleu.vv_LMUL4SEW64
vmsleu.vv_LMUL8SEW32
vmsleu.vv_LMUL8SEW64
vmsleu.vx_LMUL1SEW16
vmsleu.vx_LMUL1SEW32
vmsleu.vx_LMUL1SEW64
vmsleu.vx_LMUL1SEW8
vmsleu.vx_LMUL2SEW16
vmsleu.vx_LMUL2SEW32
vmsleu.vx_LMUL2SEW64
vmsleu.vx_LMUL2SEW8
vmsleu.vx_LMUL4SEW16
vmsleu.vx_LMUL4SEW32
vmsleu.vx_LMUL4SEW64
vmsleu.vx_LMUL8SEW32
vmsleu.vx_LMUL8SEW64

Hanging:

vmsleu.vi_LMUL4SEW8
vmsleu.vi_LMUL8SEW16
vmsleu.vi_LMUL8SEW8
vmsleu.vv_LMUL4SEW8
vmsleu.vv_LMUL8SEW16
vmsleu.vv_LMUL8SEW8
vmsleu.vx_LMUL4SEW8
vmsleu.vx_LMUL8SEW16
vmsleu.vx_LMUL8SEW8

VMSLT

Failing:

vmslt.vv_LMUL1SEW16
vmslt.vv_LMUL1SEW32
vmslt.vv_LMUL1SEW64
vmslt.vv_LMUL1SEW8
vmslt.vv_LMUL2SEW16
vmslt.vv_LMUL2SEW32
vmslt.vv_LMUL2SEW64
vmslt.vv_LMUL2SEW8
vmslt.vv_LMUL4SEW16
vmslt.vv_LMUL4SEW32
vmslt.vv_LMUL4SEW64
vmslt.vv_LMUL8SEW32
vmslt.vv_LMUL8SEW64
vmslt.vx_LMUL1SEW16
vmslt.vx_LMUL1SEW32
vmslt.vx_LMUL1SEW64
vmslt.vx_LMUL1SEW8
vmslt.vx_LMUL2SEW16
vmslt.vx_LMUL2SEW32
vmslt.vx_LMUL2SEW64
vmslt.vx_LMUL2SEW8
vmslt.vx_LMUL4SEW16
vmslt.vx_LMUL4SEW32
vmslt.vx_LMUL4SEW64
vmslt.vx_LMUL8SEW32
vmslt.vx_LMUL8SEW64

Hanging:

vmslt.vv_LMUL4SEW8
vmslt.vv_LMUL8SEW16
vmslt.vv_LMUL8SEW8
vmslt.vx_LMUL4SEW8
vmslt.vx_LMUL8SEW16
vmslt.vx_LMUL8SEW8

VMSLTU

Failing:

vmsltu.vv_LMUL1SEW16
vmsltu.vv_LMUL1SEW32
vmsltu.vv_LMUL1SEW64
vmsltu.vv_LMUL1SEW8
vmsltu.vv_LMUL2SEW16
vmsltu.vv_LMUL2SEW32
vmsltu.vv_LMUL2SEW64
vmsltu.vv_LMUL2SEW8
vmsltu.vv_LMUL4SEW16
vmsltu.vv_LMUL4SEW32
vmsltu.vv_LMUL4SEW64
vmsltu.vv_LMUL8SEW32
vmsltu.vv_LMUL8SEW64
vmsltu.vx_LMUL1SEW16
vmsltu.vx_LMUL1SEW32
vmsltu.vx_LMUL1SEW64
vmsltu.vx_LMUL1SEW8
vmsltu.vx_LMUL2SEW16
vmsltu.vx_LMUL2SEW32
vmsltu.vx_LMUL2SEW64
vmsltu.vx_LMUL2SEW8
vmsltu.vx_LMUL4SEW16
vmsltu.vx_LMUL4SEW32
vmsltu.vx_LMUL4SEW64
vmsltu.vx_LMUL8SEW32
vmsltu.vx_LMUL8SEW64

Hanging:

vmsltu.vv_LMUL4SEW8
vmsltu.vv_LMUL8SEW16
vmsltu.vv_LMUL8SEW8
vmsltu.vx_LMUL4SEW8
vmsltu.vx_LMUL8SEW16
vmsltu.vx_LMUL8SEW8

VWMACCSU

Failing:

vwmaccsu.vv_LMUL1SEW16
vwmaccsu.vv_LMUL1SEW32
vwmaccsu.vv_LMUL1SEW8
vwmaccsu.vv_LMUL2SEW16
vwmaccsu.vv_LMUL2SEW32
vwmaccsu.vv_LMUL2SEW8
vwmaccsu.vv_LMUL4SEW16
vwmaccsu.vv_LMUL4SEW32
vwmaccsu.vv_LMUL4SEW8
vwmaccsu.vx_LMUL1SEW16
vwmaccsu.vx_LMUL1SEW32
vwmaccsu.vx_LMUL1SEW8
vwmaccsu.vx_LMUL2SEW16
vwmaccsu.vx_LMUL2SEW32
vwmaccsu.vx_LMUL2SEW8
vwmaccsu.vx_LMUL4SEW16
vwmaccsu.vx_LMUL4SEW32
vwmaccsu.vx_LMUL4SEW8

VWMACCUS

Failing:

vwmaccus.vx_LMUL1SEW16
vwmaccus.vx_LMUL1SEW32
vwmaccus.vx_LMUL1SEW8
vwmaccus.vx_LMUL2SEW16
vwmaccus.vx_LMUL2SEW32
vwmaccus.vx_LMUL2SEW8
vwmaccus.vx_LMUL4SEW16
vwmaccus.vx_LMUL4SEW32
vwmaccus.vx_LMUL4SEW8

VWMACCU

Failing:

vwmaccu.vv_LMUL1SEW16
vwmaccu.vv_LMUL1SEW32
vwmaccu.vv_LMUL1SEW8
vwmaccu.vv_LMUL2SEW16
vwmaccu.vv_LMUL2SEW32
vwmaccu.vv_LMUL2SEW8
vwmaccu.vv_LMUL4SEW16
vwmaccu.vv_LMUL4SEW32
vwmaccu.vv_LMUL4SEW8
vwmaccu.vx_LMUL1SEW16
vwmaccu.vx_LMUL1SEW32
vwmaccu.vx_LMUL1SEW8
vwmaccu.vx_LMUL2SEW16
vwmaccu.vx_LMUL2SEW32
vwmaccu.vx_LMUL2SEW8
vwmaccu.vx_LMUL4SEW16
vwmaccu.vx_LMUL4SEW32
vwmaccu.vx_LMUL4SEW8

VWMACC

Failing:

vwmacc.vv_LMUL1SEW16
vwmacc.vv_LMUL1SEW32
vwmacc.vv_LMUL1SEW8
vwmacc.vv_LMUL2SEW16
vwmacc.vv_LMUL2SEW32
vwmacc.vv_LMUL2SEW8
vwmacc.vv_LMUL4SEW16
vwmacc.vv_LMUL4SEW32
vwmacc.vv_LMUL4SEW8
vwmacc.vx_LMUL1SEW16
vwmacc.vx_LMUL1SEW32
vwmacc.vx_LMUL1SEW8
vwmacc.vx_LMUL2SEW16
vwmacc.vx_LMUL2SEW32
vwmacc.vx_LMUL2SEW8
vwmacc.vx_LMUL4SEW16
vwmacc.vx_LMUL4SEW32
vwmacc.vx_LMUL4SEW8

VSEXT

Failing:

vsext.vf2_LMUL2SEW64
vsext.vf2_LMUL4SEW32
vsext.vf2_LMUL2SEW32
vsext.vf2_LMUL2SEW16
vsext.vf2_LMUL4SEW64
vsext.vf2_LMUL4SEW16
vsext.vf4_LMUL4SEW64
vsext.vf4_LMUL4SEW32
vsext.vf2_LMUL8SEW16
vsext.vf2_LMUL8SEW32
vsext.vf8_LMUL8SEW64
vsext.vf2_LMUL8SEW64
vsext.vf4_LMUL8SEW32
vsext.vf4_LMUL8SEW64

VZEXT

Failing:

vzext.vf2_LMUL4SEW32
vzext.vf2_LMUL4SEW64
vzext.vf2_LMUL4SEW16
vzext.vf8_LMUL8SEW64
vzext.vf2_LMUL8SEW32
vzext.vf2_LMUL8SEW16
vzext.vf4_LMUL8SEW64
vzext.vf2_LMUL8SEW64
vzext.vf4_LMUL8SEW32
vzext.vf4_LMUL4SEW32
vzext.vf4_LMUL4SEW64

Verification branch: main_verif_10x

Steps to recreate this issue:

1. git clone https://github.com/pulp-platform/ara.git
2. git remote add test_repo "https://github.com/10x-Engineers/ara"
3. git fetch test_repo
4. git checkout main_verif_10x
5. cd apps
6. make riscv_tests
7. cd ../hardware
8. make simv app="name of individual ELF" or make riscv_tests_simv -j4 to run regression

[mp-17]

Amazing! Thanks a lot for the huge work. We will start fixing the system as soon as possible.

[mp-17]

Unluckily, the pre-compiled toolchain was clashing with some of our system shared libraries, but I re-compiled the last gcc from the main branch, and now it works.

I hypothesize that these tests are "hardcoded" for VLEN == 4096. I tried them with Ara 4 lanes and VLEN == 4096.

I looked at the vadd.vi_LMUL1SEW8 test to see what is failing. I think there is a problem with the test; for example, the test composed of the sub-tests from 386 to 449 fails. With sew == 8 bit and VLEN == 4096, vlmax is 512 elements with LMUL == 1.

I see two problems that come from an incomplete mask data section:

1. When you load the mask vector with this line: https://github.com/10x-Engineers/ara/blob/main_verif_10x/apps/riscv-tests/isa/rv64uv/vadd.vi_LMUL1SEW8.S#L553 you are trying to load 512 B from the memory, even if the memory is initialized for only 32 B from the mask data section: https://github.com/10x-Engineers/ara/blob/main_verif_10x/apps/riscv-tests/isa/rv64uv/vadd.vi_LMUL1SEW8.S#L1214 The content of the memory after those 32 B depends depends on the other files / linker script, so the executable compiled for Spike will differ from the one for Ara (we should either use a mask load, or reduce the vl accordingly).

2. Since the mask is specified only for 256 bits (32 B), the rest of the mask is undefined / unpredictable. Maybe Spike works since at compile time gcc padded the memory after the last valid mask bits with zeroes. For this reason, the first 256 results from Ara are correct. Then, the last 256 do not correspond to the "golden" ones (we should double the size and initialization of the mask data section).

Maybe also the other tests have the same issue, but I have not checked yet.

[ghost]

Hi @mp-17 thanks for the response.

The gcc related part really was an optional one. And you assumed correctly about the configuration. I'll update on other filed issues as well that with which config ARA was built (i.e. nrLanes==4 and VLEN==4096)

What you have pointed out is correct about the failing tests. Infact, this problem is same with other tests as well. I have changed the mask and golden reference values as well by properly regenerating the tests. I have observed that now, after regeneration, all tests related to VADD instructions pass successfully. I am sure it will have impacted other tests too, so I will be updating the issue text detail soon to communicate it properly. I will then inform again (in this thread) when updated.

P.S. The new tests generated will have a mask for 4096 elements (which is a case with VLEN=4096, SEW=8, and LMUL=8) This way a mask for max. number of elements will be available and only required will be loaded and utilized in different tests.

Quswar,

[mp-17]

Thanks a lot, @quswar-abid! Please, ping us when the tests are updated to have further feedback.

Matteo

[ghost]

@mp-17 Here is an update:

I have modified the tests to have sufficient mask for all cases. The test has been generated again to have renewed golden values. Following are few of the instructions that are passing in all of its combinations (in available tests) and the rest of them are failing in few or all of their combinations. I'll update when I go through the rest of them later. Meanwhile, I'll be removing the following instructions from the issue since they are working fine.

Instructions working correctly:

vadd
vrsub
vsub
adc
vsbc
vand
vor
xor
vsll
vsra
vmax
maxu
vmin
vminu
vmul
vmulh
vmulhsu
vmulhu
vdivu
vwmul
vwmulu
vwmulsu
vmacc
vmadd
vnmsac
vnmsub
vmerge
vremu

Thanks, Quswar

[ghost]

Hi @mp-17 I have updated the list of failing and hanging tests in the issue while the list of passing tests has already been shared.

[mp-17]

Thank you very much @quswar-abid! I will try to look at the new tests asap! :-)