CopyCircuit design and ChallengeAPI

[ed255]

Currently the CopyCircuit contains a column called value. When the dest is of type CopyDataType::RlcAcc, the read rows contain read bytes, and the write rows contain the accumulated RLC of the read bytes.

This means that the column contains the RLC inputs and outputs. I fear this may break the soundness of using the Challenge API, where we need the inputs in phase n, and the RLC output in phase n+1. I can only imagine that this would be OK if all the input bytes are already in other parts of the circuits (and connected to the CopyCircuit via lookups) and are in phase n. But it seems a bit fragile?