How to to generate control signals with the compiler?

[E24066331]

trafficstars

Hi, I generated Verilog code from RTL code with the generator. Now I want to configure it for my application. But I am confused about generating the .json file with the compiler and configure it to the control memory. Is there any tutorial or example I can refer to?

Thank you!

[tancheng]

Glad to know you can generate Verilog. There is no tutorial currently but I would like to provide you some hints about how to compile it.

1. You can build the LLVM pass in the compiler folder based on the instructions.
2. For the application, only a single-loop is targeted for now. Nested-loop needs to be flattened into a single one. Benchmark lists some representative kernels that can be used for CGRA acceleration. Don't forget to modify the compiler source code to specify the function name if you target your own application kernel.
3. After generating the .json, it can be used by OpenCGRA for simulation (similar to simulation for FIR kernel). A tutorial or example will definitely help and I will try to work on it if I have time. Thank you and have fun~!

[E24066331]

Thanks for the hints! I will try to compile it as the way you said.