sunflower-embedded-system-emulator
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Sunflower Full-System Hardware Emulator and Physical System Simulator for Sensor-Driven Systems. Built-in architecture modeling of Hitachi SH (j-core), RISC-V, and more.
**Describe the bug** Reading from files in simulated binaries is not functioning correctly. **To Reproduce** Any file open/read from a simulated file should fail. **Expected behavior** TBD
Inconsistency in file manipulation flag values between newlib (cross-compilation) and glibc (native)
**Describe the bug** Common file manipulation flags such as O_CREAT have different values in newlib and native libc implementation (definitely in Linux). There operations such as creation of a file...
**Is your feature request related to a problem?** The M extension is currently missing from the RISC-V ISA.
**Describe the bug** Functions: uchar superHreadbyte(Engine *, State *S, ulong addr); ulong superHreadlong(Engine *, State *S, ulong addr); ushort superHreadword(Engine *, State *S, ulong addr); void superHwritelong(Engine *, State *S,...
**Describe the bug** In pipeline-riscv.c in function riscvstep the switch (S->riscv->P.EX.format) case is missing an option which exists in riscvfaststep. Assign @btsouts.
**Describe the bug** Decoding of uncertainty instructions is missing.
**Is your feature request related to a problem?** Histogram UP method is not currently supported in sunflower Risc-V ISA. **Describe the solution you'd like** TBD. **Describe alternatives you've considered** TBD....
**Describe the bug** There are some compiler warnings left when compiling on my system (gcc, see log for version information). **To Reproduce** Steps to reproduce the behavior: 1. Change SUNFLOWERROOT...
Improve the current state of taint analysis by also fixing the bugs of the current version. **Describe the solution you'd like** A clear and concise description of what you would...