perlindgren

You can merge as is, the width check will come later.

Good catch!

In Rust the type of the expression of an assignment is the (zero sized) unit type, not sure if there is any equivalent in Veryl, and how the translation would...

The `++` notation seems the best option, should be easy to parse and has clear intent.

I was checking the `MEMO.md` but its all in Japanese (and I don't trust automatic translation to correctly describe your intent with the describing text). Could you add an translation...

I don't know whether the test logic should reside in the `initial` block, or if there should be some other construct. As of now this won't match the current syntax...

> I agree introducing delay notation like `#10;`, as minimal support for native test description, is not so difficult. But I concern that once it is introduced, more and more...

> One more concern is scheduling semantics. Racing between variable set and get becomes problem, and native simulator [#1287](https://github.com/veryl-lang/veryl/issues/1287) may become more difficult. Instead of delay notation, clock based notation...

`#[clock(10, 10)]` defines the clock duty cycle, and `#[reset(0, 5)]` defines a reset event, active high, with a length of 5? `@reset` and `@clk` are event instances, so here first...