Use Raptor on CLEAR

[Martoni]

Is there configuration and example to develop on CLEAR FPGA with Raptor ?

https://github.com/efabless/clear/

Clear is an eFPGA generated with openFPGA and included in caravel.

[alaindargelas]

No there isn't. If you feel like it, please contribute one. The first step would be to create a CLEAR device in Raptor: https://github.com/os-fpga/Raptor/blob/2c47bb04b963becffe1e93424418fcb8721b2cf2/etc/device.xml#L2

Then check the Yosys support for the technology mapping and probably a few modifications will be needed to target that, similar to the QL support: https://github.com/os-fpga/FOEDAG_rs/blob/55cb6d9046d4373d548d0761591022bd5d90eaed/src/Compiler/CompilerRS.cpp#L45

If you engage in this project, all PRs have to come from you/others. We, at Rapid Silicon, have no bandwidth to develop this.