web-audio-api-rs
web-audio-api-rs copied to clipboard
Published
20 hours ago •
orottier
orottier
Propagate changes to node's ChannelConfig via the main message bus
To prevent out of order arrival with other node settings.
For simplicity, I left the interior mutability pattern of the channel config but instead of using atomics, a mutex is used now. This should be fixed later to take &mut references to the node's channel config.
Benchmark result:
bench_ctor
Instructions: 4544667 (-0.319943%)
L1 Accesses: 6794193 (-0.211512%)
L2 Accesses: 54318 (-0.027608%)
RAM Accesses: 61557 (No change)
Estimated Cycles: 9220278 (-0.156756%)
bench_sine
Instructions: 71026722 (-0.053588%)
L1 Accesses: 103632671 (-0.037824%)
L2 Accesses: 261581 (-1.530603%)
RAM Accesses: 62429 (-0.203018%)
Estimated Cycles: 107125591 (-0.059696%)
bench_sine_gain
Instructions: 76098817 (-0.077677%)
L1 Accesses: 111286799 (-0.057714%)
L2 Accesses: 268396 (-0.231211%)
RAM Accesses: 62654 (+0.193498%)
Estimated Cycles: 114821669 (-0.054959%)
bench_sine_gain_delay
Instructions: 151168484 (-0.077236%)
L1 Accesses: 213904468 (-0.061431%)
L2 Accesses: 550436 (-2.727138%)
RAM Accesses: 64135 (-0.017148%)
Estimated Cycles: 218901373 (-0.095399%)
bench_buffer_src
Instructions: 17607302 (-0.184938%)
L1 Accesses: 25575870 (-0.142872%)
L2 Accesses: 87295 (+0.399089%)
RAM Accesses: 100711 (-0.007943%)
Estimated Cycles: 29537230 (-0.118820%)
bench_buffer_src_delay
Instructions: 91349643 (-0.102327%)
L1 Accesses: 126389086 (-0.095819%)
L2 Accesses: 163517 (+0.447205%)
RAM Accesses: 100870 (-0.015859%)
Estimated Cycles: 130737121 (-0.090284%)
bench_buffer_src_iir
Instructions: 42046724 (+0.575439%)
L1 Accesses: 60720176 (-0.165445%)
L2 Accesses: 88103 (+1.076120%)
RAM Accesses: 100809 (+0.000992%)
Estimated Cycles: 64689006 (-0.148028%)
bench_buffer_src_biquad
Instructions: 37797743 (-0.136916%)
L1 Accesses: 53101826 (-0.046551%)
L2 Accesses: 126568 (+9.185645%)
RAM Accesses: 100947 (-0.007924%)
Estimated Cycles: 57267811 (+0.049317%)
bench_stereo_positional
Instructions: 45604273 (-0.075388%)
L1 Accesses: 68224636 (+0.295690%)
L2 Accesses: 223389 (-15.75535%)
RAM Accesses: 101018 (-0.019795%)
Estimated Cycles: 72877211 (-0.011595%)
bench_stereo_panning_automation
Instructions: 32516426 (+0.889993%)
L1 Accesses: 48770247 (+1.338844%)
L2 Accesses: 134861 (-1.121775%)
RAM Accesses: 100825 (-0.007934%)
Estimated Cycles: 52973427 (+1.215967%)
bench_analyser_node
Instructions: 39731782 (-0.137589%)
L1 Accesses: 55604072 (-0.135540%)
L2 Accesses: 180277 (-0.583999%)
RAM Accesses: 101377 (+0.012825%)
Estimated Cycles: 60053652 (-0.133548%)
![github-actions[bot] avatar](https://avatars.githubusercontent.com/in/15368?v=4 "Published by a pub.dev verified publisher"){kind=small}
Benchmark result:
bench_ctor
Instructions: 4163592 (-0.165687%)
L1 Accesses: 6254522 (+0.013864%)
L2 Accesses: 54226 (+0.014755%)
RAM Accesses: 61599 (+0.003247%)
Estimated Cycles: 8681617 (+0.011255%)
bench_audio_buffer_decode
Instructions: 7381161 (+0.003739%)
L1 Accesses: 10182422 (+0.007042%)
L2 Accesses: 28555 (-2.010912%)
RAM Accesses: 32075 (-0.021819%)
Estimated Cycles: 11447822 (-0.021467%)
bench_sine
Instructions: 69376881 (-0.105966%)
L1 Accesses: 101260156 (-0.090870%)
L2 Accesses: 263080 (+1.446034%)
RAM Accesses: 62421 (+0.003204%)
Estimated Cycles: 104760291 (-0.069900%)
bench_sine_gain
Instructions: 76892909 (-0.153063%)
L1 Accesses: 112702670 (-0.127399%)
L2 Accesses: 270570 (+0.029206%)
RAM Accesses: 62521 (No change)
Estimated Cycles: 116243755 (-0.123184%)
bench_sine_gain_delay
Instructions: 132853631 (-0.114066%)
L1 Accesses: 190764683 (-0.089848%)
L2 Accesses: 558960 (-0.438352%)
RAM Accesses: 64094 (-0.007800%)
Estimated Cycles: 195802773 (-0.093901%)
bench_buffer_src
Instructions: 16166550 (-0.430979%)
L1 Accesses: 23734463 (-0.356567%)
L2 Accesses: 87049 (-0.186901%)
RAM Accesses: 100567 (-0.009943%)
Estimated Cycles: 27689553 (-0.309973%)
bench_buffer_src_delay
Instructions: 73778410 (-0.144565%)
L1 Accesses: 104445570 (-0.110610%)
L2 Accesses: 162871 (-1.612299%)
RAM Accesses: 100715 (-0.013899%)
Estimated Cycles: 108784950 (-0.118891%)
bench_buffer_src_iir
Instructions: 39824636 (-0.248371%)
L1 Accesses: 58304910 (-0.224131%)
L2 Accesses: 90474 (+1.752216%)
RAM Accesses: 100654 (-0.007947%)
Estimated Cycles: 62280170 (-0.197846%)
bench_buffer_src_biquad
Instructions: 34974811 (-0.442383%)
L1 Accesses: 49729447 (-0.281729%)
L2 Accesses: 101942 (-7.505399%)
RAM Accesses: 100775 (-0.030752%)
Estimated Cycles: 53766282 (-0.339102%)
bench_stereo_positional
Instructions: 48035211 (-0.924667%)
L1 Accesses: 72575014 (-0.525149%)
L2 Accesses: 196598 (-20.38472%)
RAM Accesses: 100879 (-0.011894%)
Estimated Cycles: 77088769 (-0.817307%)
bench_stereo_panning_automation
Instructions: 30260956 (-0.319590%)
L1 Accesses: 45667255 (-0.275831%)
L2 Accesses: 140537 (+2.157463%)
RAM Accesses: 100687 (-0.012910%)
Estimated Cycles: 49893985 (-0.223830%)
bench_analyser_node
Instructions: 38014963 (-0.244868%)
L1 Accesses: 53381815 (-0.218325%)
L2 Accesses: 180954 (-3.528245%)
RAM Accesses: 101177 (-0.010871%)
Estimated Cycles: 57827780 (-0.259195%)
bench_hrtf_panners
Instructions: 325661004 (-0.018120%)
L1 Accesses: 569961088 (-0.014299%)
L2 Accesses: 10879716 (+0.174776%)
RAM Accesses: 120486 (+0.039024%)
Estimated Cycles: 628576678 (+0.002394%)
bench_sine_gain_with_worklet
Instructions: 77720601 (-0.185515%)
L1 Accesses: 113872767 (-0.143085%)
L2 Accesses: 273897 (-6.348153%)
RAM Accesses: 62703 (+0.006380%)
Estimated Cycles: 117436857 (-0.217395%)
running 0 tests
test result: ok. 0 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 0.00s
Benchmark result:
bench_ctor
Instructions: 2877515 (+0.012964%)
L1 Accesses: 4362480 (-0.074329%)
L2 Accesses: 27500 (+0.018185%)
RAM Accesses: 61598 (-0.006493%)
Estimated Cycles: 6655910 (-0.050456%)
bench_audio_buffer_decode
Instructions: 7370087 (-0.019819%)
L1 Accesses: 10162594 (-0.041183%)
L2 Accesses: 28394 (+1.639462%)
RAM Accesses: 32157 (+0.040443%)
Estimated Cycles: 11430059 (-0.012614%)
bench_sine
Instructions: 69159499 (-0.042253%)
L1 Accesses: 100920471 (-0.074209%)
L2 Accesses: 263138 (+0.393351%)
RAM Accesses: 62444 (+0.003203%)
Estimated Cycles: 104421701 (-0.066726%)
bench_sine_gain
Instructions: 73697991 (-0.100310%)
L1 Accesses: 107907801 (-0.141646%)
L2 Accesses: 263346 (-1.134150%)
RAM Accesses: 62544 (+0.009594%)
Estimated Cycles: 111413571 (-0.150526%)
bench_sine_gain_delay
Instructions: 107073448 (-0.159112%)
L1 Accesses: 155238470 (-0.207812%)
L2 Accesses: 486013 (+0.695735%)
RAM Accesses: 64096 (+0.017165%)
Estimated Cycles: 159911895 (-0.191053%)
bench_buffer_src
Instructions: 18550249 (-0.087507%)
L1 Accesses: 27271671 (-0.220807%)
L2 Accesses: 132941 (-2.400687%)
RAM Accesses: 100650 (-0.002981%)
Estimated Cycles: 31459126 (-0.243551%)
bench_buffer_src_delay
Instructions: 75812128 (-0.142865%)
L1 Accesses: 107298570 (-0.215322%)
L2 Accesses: 330227 (+2.780639%)
RAM Accesses: 100800 (+0.000992%)
Estimated Cycles: 112477705 (-0.165829%)
bench_buffer_src_iir
Instructions: 80622520 (-0.075791%)
L1 Accesses: 115219177 (-0.120914%)
L2 Accesses: 132816 (+0.864229%)
RAM Accesses: 100730 (+0.001986%)
Estimated Cycles: 119408807 (-0.111864%)
bench_buffer_src_biquad
Instructions: 58365111 (-0.174472%)
L1 Accesses: 78936571 (-0.254821%)
L2 Accesses: 195073 (+0.143742%)
RAM Accesses: 100864 (+0.022808%)
Estimated Cycles: 83442176 (-0.238465%)
bench_stereo_positional
Instructions: 97564783 (-0.119619%)
L1 Accesses: 142975853 (-0.208615%)
L2 Accesses: 414064 (+0.119206%)
RAM Accesses: 100974 (+0.013867%)
Estimated Cycles: 148580263 (-0.198781%)
bench_stereo_panning_automation
Instructions: 29899548 (-0.166147%)
L1 Accesses: 45101094 (-0.312481%)
L2 Accesses: 142213 (+5.144357%)
RAM Accesses: 100758 (+0.001985%)
Estimated Cycles: 49338689 (-0.215418%)
bench_analyser_node
Instructions: 37716064 (-0.142042%)
L1 Accesses: 52917680 (-0.243381%)
L2 Accesses: 180180 (-1.039149%)
RAM Accesses: 101248 (+0.000988%)
Estimated Cycles: 57362260 (-0.240920%)
bench_hrtf_panners
Instructions: 320495262 (-0.006466%)
L1 Accesses: 563012817 (-0.013867%)
L2 Accesses: 10892133 (+0.261125%)
RAM Accesses: 120843 (-0.069463%)
Estimated Cycles: 621702987 (+0.009783%)
bench_sine_gain_with_worklet
Instructions: 74510846 (-0.139763%)
L1 Accesses: 109063609 (-0.159060%)
L2 Accesses: 269848 (-6.995468%)
RAM Accesses: 62726 (-0.001594%)
Estimated Cycles: 112608259 (-0.243856%)
running 0 tests
test result: ok. 0 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 0.00s