Morten Borup Petersen
Morten Borup Petersen
This commit introduces `seq.hlmem` and ops for providing structural access to the defined memory ports. Please see the updated `RationaleSeq.md` for further info. Edit: still trying to triage the `pure...
Following the 21/09/2022 ODM, a consensus was reached on moving forward with supporting zero-width values in the core RTL dialects. If you are aware of any location which currently performs...
Luckily a fairly minor change due to ExportVerilog already have good support for emitting i0-typed expressions as comments. This commit ensures that `hw.array_get` for singleton arrays may be emitted legally,...
(under the assumption that `i0` support for `isHWIntegerType` is merged) emitting `sv.passign` with `i0` wires results in invalid SV: ```mlir hw.module @Top(%arg0: i0, %clk: i1) -> (out: i0) { %0...
Currently, unwrap operators will create default names for wrap/unwrap ops: ```mlir hw.module @handshake_store_in_ui64_ui32_out_ui32_ui64(%addrIn0: !esi.channel, %dataIn: !esi.channel, %ctrl: !esi.channel) -> (dataToMem: !esi.channel, addrOut0: !esi.channel) { %rawOutput, %valid = esi.unwrap.vr %addrIn0, %2...
Work on #2219 (#2909 related), and motivated by `HandshakeToHW` wanting to delegate pruning of all data-less logic to after the lowering phase, instead of having to sprinkle special-case logic all...
This is a tracking issue for the reimplementation of HandshakeToFIRRTL to a HW/ESI-based implementation: * Operators * [x] Mux * [ ] Conditional branch * [ ] Buffer * [x]...
Currently, test runs in CI only shows a passed/failed/unsupported split (https://github.com/llvm/circt/actions/runs/3045345694/jobs/4906793030#step:7:68). In case a test is picked up as unsupported, but one actually would've liked for CI to check it,...
`std-to-handshake` technically contains it's own attempt at maxSSA through its liveness analysis/merge op insertion (https://github.com/llvm/circt/blob/main/lib/Conversion/StandardToHandshake/StandardToHandshake.cpp#L576). However, issues remain in the implementation, resulting in some circuits being processed incorrectly (todo: add...
Currently, different enums with identical field names: ```mlir hw.type_scope @fsm_enum_typedecls { hw.typedecl @M2_state_t : !hw.enum hw.typedecl @M1_state_t : !hw.enum } ``` Will export as: ```sv typedef enum {A, B} M2_state_t;...