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Published 20 hours ago • verified publisher icon llvm

LLVM ERROR: RV64 target requires an RV64 CPU

Open houhuawei23 opened this issue 1 year ago • 2 comments

excuse me, i am new to llvm, but i have some difficulties. how can i convert llvm ir file to riscv64 assembly code? im in x86 platform, using ubuntu 22.04, i try to use ./llc -march=riscv64 test.ll but it give error:

'x86-64' is not a recognized processor for this target (ignoring processor)
'+cx8' is not a recognized feature for this target (ignoring feature)
'+fxsr' is not a recognized feature for this target (ignoring feature)
'+mmx' is not a recognized feature for this target (ignoring feature)
'+sse' is not a recognized feature for this target (ignoring feature)
'+sse2' is not a recognized feature for this target (ignoring feature)
'+x87' is not a recognized feature for this target (ignoring feature)
'x86-64' is not a recognized processor for this target (ignoring processor)
'+cx8' is not a recognized feature for this target (ignoring feature)
'+fxsr' is not a recognized feature for this target (ignoring feature)
'+mmx' is not a recognized feature for this target (ignoring feature)
'+sse' is not a recognized feature for this target (ignoring feature)
'+sse2' is not a recognized feature for this target (ignoring feature)
'+x87' is not a recognized feature for this target (ignoring feature)
LLVM ERROR: RV64 target requires an RV64 CPU
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.      Program arguments: ./llc -march=riscv64 test.ll
1.      Running pass 'Function Pass Manager' on module 'test.ll'.
2.      Running pass 'Expand large div/rem' on function '@main'
 #0 0x000056420e885d30 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (./llc+0x3474d30)
 #1 0x000056420e8832fe SignalHandler(int) Signals.cpp:0:0
 #2 0x00007f3a4f41f520 (/lib/x86_64-linux-gnu/libc.so.6+0x42520)
 #3 0x00007f3a4f4739fc __pthread_kill_implementation ./nptl/./nptl/pthread_kill.c:44:76
 #4 0x00007f3a4f4739fc __pthread_kill_internal ./nptl/./nptl/pthread_kill.c:78:10
 #5 0x00007f3a4f4739fc pthread_kill ./nptl/./nptl/pthread_kill.c:89:10
 #6 0x00007f3a4f41f476 gsignal ./signal/../sysdeps/posix/raise.c:27:6
 #7 0x00007f3a4f4057f3 abort ./stdlib/./stdlib/abort.c:81:7
 #8 0x000056420ba042c4 llvm::RISCVISAInfo::updateCombination() (.cold) RISCVISAInfo.cpp:0:0
 #9 0x000056420e7cdc6e (./llc+0x33bcc6e)
#10 0x000056420d3d2936 llvm::RISCVFeatures::validate(llvm::Triple const&, llvm::FeatureBitset const&) (./llc+0x1fc1936)
#11 0x000056420cb09ef8 llvm::RISCVSubtarget::initializeSubtargetDependencies(llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::StringRef, llvm::StringRef) (./llc+0x16f8ef8)
#12 0x000056420cb0a149 llvm::RISCVSubtarget::RISCVSubtarget(llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::StringRef, llvm::StringRef, unsigned int, unsigned int, llvm::TargetMachine const&) (./llc+0x16f9149)
#13 0x000056420cb0f525 llvm::RISCVTargetMachine::getSubtargetImpl(llvm::Function const&) const (./llc+0x16fe525)
#14 0x000056420d85d6ec (anonymous namespace)::ExpandLargeDivRemLegacyPass::runOnFunction(llvm::Function&) ExpandLargeDivRem.cpp:0:0
#15 0x000056420ded2b8a llvm::FPPassManager::runOnFunction(llvm::Function&) (./llc+0x2ac1b8a)
#16 0x000056420ded2d14 llvm::FPPassManager::runOnModule(llvm::Module&) (./llc+0x2ac1d14)
#17 0x000056420ded3774 llvm::legacy::PassManagerImpl::run(llvm::Module&) (./llc+0x2ac2774)
#18 0x000056420bb06fca compileModule(char**, llvm::LLVMContext&) llc.cpp:0:0
#19 0x000056420ba15d2e main (./llc+0x604d2e)
#20 0x00007f3a4f406d90 __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:58:16
#21 0x00007f3a4f406e40 call_init ./csu/../csu/libc-start.c:128:20
#22 0x00007f3a4f406e40 __libc_start_main ./csu/../csu/libc-start.c:379:5
#23 0x000056420bafe525 _start (./llc+0x6ed525)
[1]    152291 IOT instruction (core dumped)  ./llc -march=riscv64 test.ll

houhuawei23 avatar Mar 24 '24 12:03 houhuawei23

@llvm/issue-subscribers-backend-risc-v

Author: HOU HUA WEI (houhuawei23)

excuse me, i am new to llvm, but i have some difficulties. how can i convert llvm ir file to riscv64 assembly code? im in x86 platform, using ubuntu 22.04, i try to use ./llc -march=riscv64 test.ll but it give error:

'x86-64' is not a recognized processor for this target (ignoring processor)
'+cx8' is not a recognized feature for this target (ignoring feature)
'+fxsr' is not a recognized feature for this target (ignoring feature)
'+mmx' is not a recognized feature for this target (ignoring feature)
'+sse' is not a recognized feature for this target (ignoring feature)
'+sse2' is not a recognized feature for this target (ignoring feature)
'+x87' is not a recognized feature for this target (ignoring feature)
'x86-64' is not a recognized processor for this target (ignoring processor)
'+cx8' is not a recognized feature for this target (ignoring feature)
'+fxsr' is not a recognized feature for this target (ignoring feature)
'+mmx' is not a recognized feature for this target (ignoring feature)
'+sse' is not a recognized feature for this target (ignoring feature)
'+sse2' is not a recognized feature for this target (ignoring feature)
'+x87' is not a recognized feature for this target (ignoring feature)
LLVM ERROR: RV64 target requires an RV64 CPU
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.      Program arguments: ./llc -march=riscv64 test.ll
1.      Running pass 'Function Pass Manager' on module 'test.ll'.
2.      Running pass 'Expand large div/rem' on function '@<!-- -->main'
 #<!-- -->0 0x000056420e885d30 llvm::sys::PrintStackTrace(llvm::raw_ostream&amp;, int) (./llc+0x3474d30)
 #<!-- -->1 0x000056420e8832fe SignalHandler(int) Signals.cpp:0:0
 #<!-- -->2 0x00007f3a4f41f520 (/lib/x86_64-linux-gnu/libc.so.6+0x42520)
 #<!-- -->3 0x00007f3a4f4739fc __pthread_kill_implementation ./nptl/./nptl/pthread_kill.c:44:76
 #<!-- -->4 0x00007f3a4f4739fc __pthread_kill_internal ./nptl/./nptl/pthread_kill.c:78:10
 #<!-- -->5 0x00007f3a4f4739fc pthread_kill ./nptl/./nptl/pthread_kill.c:89:10
 #<!-- -->6 0x00007f3a4f41f476 gsignal ./signal/../sysdeps/posix/raise.c:27:6
 #<!-- -->7 0x00007f3a4f4057f3 abort ./stdlib/./stdlib/abort.c:81:7
 #<!-- -->8 0x000056420ba042c4 llvm::RISCVISAInfo::updateCombination() (.cold) RISCVISAInfo.cpp:0:0
 #<!-- -->9 0x000056420e7cdc6e (./llc+0x33bcc6e)
#<!-- -->10 0x000056420d3d2936 llvm::RISCVFeatures::validate(llvm::Triple const&amp;, llvm::FeatureBitset const&amp;) (./llc+0x1fc1936)
#<!-- -->11 0x000056420cb09ef8 llvm::RISCVSubtarget::initializeSubtargetDependencies(llvm::Triple const&amp;, llvm::StringRef, llvm::StringRef, llvm::StringRef, llvm::StringRef) (./llc+0x16f8ef8)
#<!-- -->12 0x000056420cb0a149 llvm::RISCVSubtarget::RISCVSubtarget(llvm::Triple const&amp;, llvm::StringRef, llvm::StringRef, llvm::StringRef, llvm::StringRef, unsigned int, unsigned int, llvm::TargetMachine const&amp;) (./llc+0x16f9149)
#<!-- -->13 0x000056420cb0f525 llvm::RISCVTargetMachine::getSubtargetImpl(llvm::Function const&amp;) const (./llc+0x16fe525)
#<!-- -->14 0x000056420d85d6ec (anonymous namespace)::ExpandLargeDivRemLegacyPass::runOnFunction(llvm::Function&amp;) ExpandLargeDivRem.cpp:0:0
#<!-- -->15 0x000056420ded2b8a llvm::FPPassManager::runOnFunction(llvm::Function&amp;) (./llc+0x2ac1b8a)
#<!-- -->16 0x000056420ded2d14 llvm::FPPassManager::runOnModule(llvm::Module&amp;) (./llc+0x2ac1d14)
#<!-- -->17 0x000056420ded3774 llvm::legacy::PassManagerImpl::run(llvm::Module&amp;) (./llc+0x2ac2774)
#<!-- -->18 0x000056420bb06fca compileModule(char**, llvm::LLVMContext&amp;) llc.cpp:0:0
#<!-- -->19 0x000056420ba15d2e main (./llc+0x604d2e)
#<!-- -->20 0x00007f3a4f406d90 __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:58:16
#<!-- -->21 0x00007f3a4f406e40 call_init ./csu/../csu/libc-start.c:128:20
#<!-- -->22 0x00007f3a4f406e40 __libc_start_main ./csu/../csu/libc-start.c:379:5
#<!-- -->23 0x000056420bafe525 _start (./llc+0x6ed525)
[1]    152291 IOT instruction (core dumped)  ./llc -march=riscv64 test.ll

llvmbot avatar Mar 24 '24 14:03 llvmbot

Please use -mtriple=riscv64.

dtcxzyw avatar Mar 24 '24 14:03 dtcxzyw

You need to start with LLVM IR created for RISC-V architecture. You cannot do this via generating x86-64 LLVM IR and then changing the target triple

asl avatar Mar 24 '24 16:03 asl

llvm ir file generated by clang -S -emit-llvm has target triple and target datalayout information. I should generate llvm ir clang -S -emit-llvm --target=riscv64correspond to llc -march=riscv64 Thanks a lot.

houhuawei23 avatar Mar 25 '24 00:03 houhuawei23