[AArch64] a redundant mov instruction compare to gcc

[vfdff]

test case https://gcc.godbolt.org/z/5dTff475M

unsigned __int128 mul64 (unsigned __int128 mul0,
                         unsigned __int128 mul1)
{
    return (mul0 & 0xffffffffffffffff) * (mul1 & 0xffffffffffffffff);
}

• llvm has a redundant mov instruction, can be fold into mul x0, x2, x0 if issue the umulh one step first.

        mul     x8, x2, x0
        umulh   x1, x2, x0
        mov     x0, x8   -- redundant ?